C.-P. Su

Low-power embedded memory architecture design for SOC

Cheng-Wen Wu, Tian-Sheuan Chang, Chih-Tsun Huang, 2002 .

DFT methodologies for a communications processor core

Chih-Tsun Huang, C.-P. Su, C.-W. Wu, 1998 .

Graph-based power-constrained test scheduling for SOC

C.-P. Su, C.-W. Wu, 2002 .

A test controller for system-on-chip designs with test wrappers

Jin-Fu Li, H.-J. Huang, C.-P. Su, 2001 .

Test wrapper design automation for system-on-chip

C.-P. Su, C.-Y. Hwang, Cheng-Wen Wu, 2001 .

A word-based RSA public-key crypto-processor core

C.-P. Su, Cheng-Wen Wu, Y.-C. Lin, 2001 .

A true random generator design

Chih-Tsun Huang, Cheng-Wen Wu, C.-P. Su, 2002 .