Shrikanth Ganapathy

发表

A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance

Dan Alexandrescu, Enrico Costenaro, Antonio Rubio, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Assessing the Effects of Low Voltage in Branch Prediction Units

Dimitris Gizopoulos, John Kalamatianos, George Papadimitriou, 2019, 2019 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

Analysis and Characterization of Ultra Low Power Branch Predictors

Dimitris Gizopoulos, John Kalamatianos, George Papadimitriou, 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD).

iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches

Antonio Rubio, Ramon Canal, Antonio González, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells

Antonio Rubio, Ramon Canal, Antonio González, 2011, GLSVLSI '11.

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU

Minyi Guo, Yao Lu, Zhigang Mao, 2013, ISCA.

Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors

Antonio Rubio, Ramon Canal, Antonio González, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

MODEST: A model for energy estimation under spatio-temporal variability

Antonio Rubio, Ramon Canal, Antonio González, 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

Reliability in the face of variability in nanometer embedded memories

Shrikanth Ganapathy, Shrikanth Ganapathy, 2014 .

On characterizing near-threshold SRAM failures in FinFET technology

John Kalamatianos, Steven Raasch, Shrikanth Ganapathy, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Energy vs. reliability trade-offs exploration in biomedical ultra-low power devices

David Atienza, Pablo García Del Valle, Andreas Peter Burg, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Effectiveness of hybrid recovery techniques on parametric failures

Antonio Rubio, Ramon Canal, Antonio González, 2013, International Symposium on Quality Electronic Design (ISQED).

INFORMER: An integrated framework for early-stage memory robustness analysis

Dan Alexandrescu, Enrico Costenaro, Antonio Rubio, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Variability-aware design space exploration of embedded memories

Andreas Peter Burg, Georgios Karakonstantis, Shrikanth Ganapathy, 2014, 2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI).

On the effectiveness of hybrid mechanisms on reduction of parametric failures in caches

Antonio María González Colás, Jose Antonio Rubio Sola, Shrikanth Ganapathy, 2011 .

Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability

Antonio Rubio, Ramon Canal, Antonio González, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system

Karthik Chandrasekar, Madhavan Manivannan, Shrikanth Ganapathy, 2008, 2008 IEEE International Symposium on Parallel and Distributed Processing.

Approximate computing with unreliable dynamic memories

Andreas Peter Burg, Georgios Karakonstantis, Adam Teman, 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

Mitigating the impact of faults in unreliable memories for error-resilient applications

Andreas Peter Burg, Georgios Karakonstantis, Adam Teman, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells

Antonio María González Colás, Jose Antonio Rubio Sola, Shrikanth Ganapathy, 2010 .

Design for Testability of Functional Cores in High Performance Node Architectures

Karthik Chandrasekar, Shrikanth Ganapathy, Nagarajan Venkateswaran, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells

Antonio Rubio, Ramon Canal, Antonio González, 2012, Integr..

Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST

Bradford M. Beckmann, John Kalamatianos, Steven Raasch, 2019, 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA).

A Method for Hiding the Increased Non-Volatile Cache Read Latency pdf

Josep Torrellas, John Kalamatianos, Apostolos Kokolis, 2021, ArXiv.