N. Akiyama

High Speed Data Output Circuit Techniques for a 17 ns 4 Mbit BiCMOS DRAM

Masahiro Yoshida, Masayuki Nakamura, Toshio Maeda, 1992 .

WPM 3.6: A 17ns 4Mb BiCMOS DRAM

Masahiro Yoshida, Masayuki Nakamura, Jun Murata, 1990 .

A 17ns 4Mb BICMOS DRAM

Masahiro Yoshida, Masayuki Nakamura, Toshio Maeda, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

System in Package (SiP) With Reduced Parasitic Inductance for Future Voltage Regulator

M. Shiraishi, T. Uno, T. Hashimoto, 2009, IEEE Transactions on Power Electronics.

A System-in-Package (SiP) With Mounted Input Capacitors for Reduced Parasitic Inductances in a Voltage Regulator

H. Akagi, T. Uno, T. Hashimoto, 2010, IEEE Transactions on Power Electronics.

A Cu-Plate-Bonded System-in-Package (SiP) With Low Spreading Resistance of Topside Electrodes for Voltage Regulators

Hirofumi Akagi, Tetsuya Kawashima, Noboru Akiyama, 2010, IEEE transactions on power electronics.