Shashank Raghuraman

Does gate count matter? Hardware effciency of logic-minimization techniques for cryptographic primitives

L. Nazhandali, Shashank Raghuraman, 2019 .

Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA

Amit Acharyya, Swati Bhardwaj, Shashank Raghuraman, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation

Shashank Raghuraman, Shashank Raghuraman, 2019 .

Impact of System-on-Chip Integration of AEAD Ciphers

Leyla Nazhandali, Shashank Raghuraman, L. Nazhandali, 2020, IACR Cryptol. ePrint Arch..

Coordinate rotation and vector cross product based hardware accelerator for nD FastICA

Amit Acharyya, Swati Bhardwaj, Shashank Raghuraman, 2017, 2017 European Conference on Circuit Theory and Design (ECCTD).