Ashutosh Sinha

A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS

Pervez M. Aziz, Tony Huynh, Lijun Li, 2011, 2011 IEEE International Solid-State Circuits Conference.

Mapping the information flow through shiprepair activities

Ashutosh Sinha, George Bruce, Karl Ward, 2006 .

A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS

Pervez M. Aziz, Lijun Li, Hiroshi Kimura, 2014, IEEE Journal of Solid-State Circuits.

Acceptance testing and quality assurance of Simulix Evolution radiotherapy simulator

Ashutosh Sinha, Navin Singh, Om Prakash Gurjar, 2015 .

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

Amaresh Malipatil, Hiroshi Kimura, Lijun Li, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Analog circuit and device interaction in high-speed SerDes design in 16nm FinFET CMOS technology

Freeman Zhong, Ashutosh Sinha, 2014, 2014 IEEE International Electron Devices Meeting.