M. Shirakawa

A 56-nm CMOS 99-${\hbox {mm}}^{2} $ 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput

Yan Li, T. Kamei, S. Tanaka, 2007, IEEE Journal of Solid-State Circuits.

A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor

I. Takayanagi, M. Shirakawa, J. Moholt, 2005, IEEE Journal of Solid-State Circuits.

A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput

T. Kamei, S. Tanaka, Y. Watanabe, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A 1 1/4 inch 8.3M pixel digital output CMOS APS for UDTV application

I. Takayanagi, M. Shirakawa, J. Moholt, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

Fabrication and characterization of a CeO2 buffer layer on c-plane and tilt-c-plane sapphire substrates

Masashi Mukaida, M. Shirakawa, Masanobu Kusunoki, 2003 .