M. Gerhardt

Cellular Automata Simulating the Evolution of Structure Through the Synchronization of Oscillators

A. W. M. Dress, M. Gerhardt, H. Schuster, 1988 .

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

G. Burbach, D. Greenlaw, S.F. Huang, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Multiple Stress Memorization In Advanced SOI CMOS Technologies

M. Gerhardt, T. Feudel, M. Horstmann, 2007, 2007 IEEE Symposium on VLSI Technology.

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

D. Greenlaw, H.-J. Engelmann, N. Kepler, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..