Ed F. Deprettere

发表

A parallel subspace algorithm for adaptive direction of arrival estimation

Ed F. Deprettere, Marc Moonen, F Vanpoucke, 1992 .

Design of a concurrent computer for solving systems of linear equations

Ed F. Deprettere, K. Jainandunsing, 1988, ISCA '88.

Analysis and modeling of sequential iterative algorithms for parallel and pipeline implementations

Ed F. Deprettere, J. Bu, 1988, 1988., IEEE International Symposium on Circuits and Systems.

Laura: Leiden Architecture Research and Exploration Tool

Ed F. Deprettere, Bart Kienhuis, Todor Stefanov, 2003, FPL.

Example of combined algorithm development and architecture design

Ed F. Deprettere, 1992, Optics & Photonics.

A parallel system for photo realistic artificial scene rendering

Ed F. Deprettere, Gerben J. Hekstra, Li-Sheng Shen, 1994, Proceedings of IEEE International Conference on Application Specific Array Processors (ASSAP'94).

Digital Signal Processing Labs Philips Research Labs, Eindhoven, The Netherlands

Ed F. Deprettere, Gerben J. Hekstra, 2016 .

Y-Chart Based System Level Performance Analysis: An M-JPEG Case Study

Ed F. Deprettere, Todor Stefanov, Pieter van der Wolf, 2000 .

Multi-processor system design with ESPAM

Ed F. Deprettere, Todor Stefanov, Hristo Nikolov, 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

Algorithmic transformation techniques for efficient exploration of alternative application instances

Ed F. Deprettere, Bart Kienhuis, Todor Stefanov, 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

Synthesis and fixed-point implementation of pipelined true orthogonal filters

Ed F. Deprettere, 1983, ICASSP.

Parallel architecture for a pel-recursive motion estimation algorithm

Ed F. Deprettere, E. D. Frimout, J. N. Driessen, 1992 .

Compilation from Matlab to process networks realised in FPGA

Ed F. Deprettere, Bart Kienhuis, T. Harriss, 2001 .

Annihilation-reordering look-ahead pipelined CORDIC-based RLS adaptive filters and their application to adaptive beamforming

Keshab K. Parhi, Ed F. Deprettere, Jun Ma, 2000, IEEE Trans. Signal Process..

Parallel filter structures for RLS-type blind equalization algorithms

Ed F. Deprettere, Marc Moonen, M. Moonen, 1995, Optics & Photonics.

Architecture exploration of a large scale system

Ed F. Deprettere, Sylvain Alliot, 2004, Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004..

Real time application of the floating point pipeline CORDIC processor in massive-parallel pipelined DSP algorithms

Ed F. Deprettere, Jichun Bu, A. A. de Lange, 1990, International Conference on Acoustics, Speech, and Signal Processing.

On the (Re-)Use of IP-Components in Re-configurable Platforms

Ed F. Deprettere, Sylvain Alliot, Jérôme Lemaitre, 2004, SAMOS.

Pitch synchronous modulated lapped transform of the linear prediction residual of speech

Ed F. Deprettere, Huimin Yang, Hongyi Chen, 1998, ICSP '98. 1998 Fourth International Conference on Signal Processing (Cat. No.98TH8344).

Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS

Ed F. Deprettere, Jürgen Teich, Stamatis Vassiliadis, 2002 .

Multidimensional Dataflow Graphs

Ed F. Deprettere, Joachim Keinert, 2013, Handbook of Signal Processing Systems.

Dynamic and Multidimensional Dataflow Graphs

Ed F. Deprettere, Shuvra S. Bhattacharyya, Joachim Keinert, 2010, Handbook of Signal Processing Systems.

Systematic and Automated Multiprocessor System Design, Programming, and Implementation

Ed F. Deprettere, Todor Stefanov, Hristo Nikolov, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Translating Imperative Affine Nested Loop Programs into Process Networks

Ed F. Deprettere, Bart Kienhuis, Edwin Rijpkema, 2002, Embedded Processor Design Challenges.

Architectural synthesis of large, nearly regular algorithms: design trajectory and environment

Ed F. Deprettere, Patrick Dewilde, 1991 .

Daedalus: Toward composable multimedia MP-SoC design

Ed F. Deprettere, Andy D. Pimentel, Todor Stefanov, 2008, 2008 45th ACM/IEEE Design Automation Conference.

A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach

Ed F. Deprettere, Bart Kienhuis, Pieter van der Wolf, 2001, Embedded Processor Design Challenges.

On the Modeling of Intra-task Parallelism in Task-level Parallel Embedded Systems

Ed F. Deprettere, Shuvra S. Bhattacharyya, Andy D. Pimentel, 2002 .

A Novel VLSI System Of Linear Equations Solver For Real-Time Signal Processing

Ed F. Deprettere, Kishan Jainandunsing, 1986, Optics & Photonics.

Jacobi-specific processor arrays

Ed F. Deprettere, Gerben J. Hekstra, Hylke W. van Dijk, 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

Robust exponential modeling of audio signals

Ed F. Deprettere, Richard Heusdens, Joost Nieuwenhuijse, 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

Parameterized Looped Schedules for Compact Representation of Execution Sequences in DSP Hardware and Software Implementation

Ed F. Deprettere, Bart Kienhuis, Shuvra S. Bhattacharyya, 2007, IEEE Transactions on Signal Processing.

High level modeling for parallel executions of nested loop algorithms

Ed F. Deprettere, Bart Kienhuis, Paul Lieverse, 2000, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors.

A strategy for determining a Jacobi specific dataflow processor

Ed F. Deprettere, Gerben J. Hekstra, Edwin Rijpkema, 1997, Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors.

Azimuth and elevation computation in high resolution DOA estimation

Ed F. Deprettere, Alle-Jan van der Veen, P. Bas Ober, 1992, IEEE Trans. Signal Process..

Deriving Process Networks from Nested Loop Algorithms

Ed F. Deprettere, Bart Kienhuis, Edwin Rijpkema, 2000, Parallel Process. Lett..

Pipelined CORDIC based QRD-MVDR adaptive beamforming

Keshab K. Parhi, Ed F. Deprettere, Jun Ma, 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μ-rotations

Keshab K. Parhi, Ed F. Deprettere, Jun Ma, 2000, IEEE Trans. Signal Process..

Floating point Cordic

Ed F. Deprettere, Gerben J. Hekstra, E. Deprettere, 1993, Proceedings of IEEE 11th Symposium on Computer Arithmetic.

Algorithms and Parallel VLSI Architectures: Tutorials

Ed F. Deprettere, A. J. Van der Veen, 1991 .

A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs

Ed F. Deprettere, Andy D. Pimentel, Todor Stefanov, 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips

Ed F. Deprettere, Todor Stefanov, Hristo Nikolov, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Deriving efficient control in Process Networks with Compaan/Laura

Alexandru Turjan, Ed F. Deprettere, Bart Kienhuis, 2008, Int. J. Embed. Syst..

An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures

Ed F. Deprettere, Bart Kienhuis, Pieter van der Wolf, 1997, ASAP.

System level design with SPADE: an M-JPEG case study

Ed F. Deprettere, Todor Stefanov, Pieter van der Wolf, 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

Compilation from Matlab to Process Networks

Ed F. Deprettere, Bart Kienhuis, Edwin Rypkema, 1999 .

Approach for the determination of a Jacobi specific dataflow processor

Ed F. Deprettere, Gerben J. Hekstra, Edwin Rypkema, 1997, Optics & Photonics.

Subband filtering: Cordic modulation and systolic quadrature mirror filter tree

Ed F. Deprettere, Richard Heusdens, Hendrik Theunis, 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).

Automated Integration of Dedicated Hardwired IP Cores in Heterogeneous MPSoCs Designed with ESPAM

Ed F. Deprettere, Todor Stefanov, Hristo Nikolov, 2008, EURASIP J. Embed. Syst..

A Parallel-Pipelined Multiprocessor System for the Radiosity Method

Ed F. Deprettere, Li-Sheng Shen, 1992, Eurographics Workshop on Graphics Hardware.

Introduction to Mastering Cell BE and GPU Execution Platforms

Ed F. Deprettere, Ana Lucia Varbanescu, 2009, SAMOS.

A floating point vectoring algorithm based on fast rotations

Ed F. Deprettere, Kees-Jan van der Kolk, Jeong-A Lee, 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.

Domain-Specific Processors : Systems, Architectures, Modeling, and Simulation

Ed F. Deprettere, Shuvra S. Bhattacharyya, Jörgen Teich, 2003 .

FPL-3E: Towards Language Support for Reconfigurable Packet Processing

Ed F. Deprettere, Herbert Bos, Claudiu Zissulescu, 2005, SAMOS.

Fast and accurate multiprocessor architecture exploration with symbolic programs

Ed F. Deprettere, Erwin A. de Kock, Pieter van der Wolf, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

A fully pipelined RLS-based array for channel equalization

Ed F. Deprettere, Marc Moonen, 1996, J. VLSI Signal Process..

Perceptual entropy rate estimates for the phonemes of American English

Ed F. Deprettere, W. Bastiaan Kleijn, Vincent van de Laar, 1997, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.

Exploring Embedded-Systems Architectures with Artemis

Ed F. Deprettere, Andy D. Pimentel, Louis O. Hertzberger, 2001, Computer.

Behavioral specification of control interface for signal processing applications

Ed F. Deprettere, Sylvain Alliot, Jérôme Lemaitre, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

System design using Khan process networks: the Compaan/Laura approach

Alexandru Turjan, Ed F. Deprettere, Bart Kienhuis, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Multi-pulse and regular-pulse LP coding of images

Ed F. Deprettere, C. Horne, 1987, ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing.

DERIVING PROCESS NETWORKS FROM NESTED LOOP ALGORITHMS

Ed F. Deprettere, Bart Kienhuis, Edwin Rijpkema, 2000 .

A VLSI system architecture for high-speed radiative transfer 3D image synthesis

Ed F. Deprettere, Jichun Bu, E. Deprettere, 1989, The Visual Computer.

Pipelining of cordic based IIR digital filters

Keshab K. Parhi, Ed F. Deprettere, Jun Ma, 1997, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.

A design methodology for fixed-size systolic arrays

Ed F. Deprettere, P. Dewilde, J. Bu, 1990, [1990] Proceedings of the International Conference on Application Specific Array Processors.

Multiscale nonlinear system modeling using wavelet networks

Ed F. Deprettere, Yi Yu, Shaohua Tan, 1996, Optics & Photonics.

The Artemis Architecture Workbench

Ed F. Deprettere, Stamatis Vassiliadis, Andy D. Pimentel, 2000 .

A Floating Point Vectoring Algorithm Based on Fast Rotations

Ed F. Deprettere, Jeong-A Lee, Kees-Jan van der Kolk, 2000, J. VLSI Signal Process..

A VLSI System Architecture for High-Speed Radiative Transfer 3D Image Synthesis

Ed F. Deprettere, Jichun Bu, 1987, Eurographics.

An efficient method for modelling VLSI interconnections

Ed F. Deprettere, Patrick Dewilde, H. Nelis, 1989 .

Approximate Inversion Of Positive Definite Matrices, Specified On A Multiple Band

Ed F. Deprettere, Patrick Dewilde, H. Nelis, 1988, Optics & Photonics.

Experimental evaluation of different approaches to the multi-pulse coder

Ed F. Deprettere, Peter Kroon, 1984, ICASSP.

Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures

Ed F. Deprettere, Laurens Bierens, 1998, J. VLSI Signal Process..

A model for the high-level description and simulation of VLSI networks

Ed F. Deprettere, Patrick Dewilde, A. J. van der Hoeven, 1990, IEEE Micro.

Regular excitation reduction for effective and efficient LP-coding of speech

Ed F. Deprettere, P. Kroon, 1985, ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing.

Scalable parallel processor array for Jacobi-type matrix computations

Ed F. Deprettere, Gerben J. Hekstra, Hylke W. van Dijk, 1995, Integr..

A Parallel VLSI Direction Finding Algorithm

Ed F. Deprettere, Alle-Jan van der Veen, 1988, Optics & Photonics.

A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems

Ed F. Deprettere, Pieter van der Wolf, Kees A. Vissers, 2001, J. VLSI Signal Process..

A Hardware Algorithm for Fast Realistic Image Synthesis

Ed F. Deprettere, Patrick Dewilde, A. C. Yilmaz, 1989, Advances in Computer Graphics Hardware.

Algorithms and parallel VLSI architectures : lectures and tutorials presented at (proceedings of) the International Workshop on Algorithms and Parallel VLSI Architectures, Abbaye des Prémontrés, Pont-à-Mousson, France, June 10-16, 1990

Ed F. Deprettere, Alle-Jan van der Veen, Parallel Vlsi Architectures, 1991 .

Special session on "aspects of Cyber-Physical Systems"

Ed F. Deprettere, 2012, ICSAMOS.

Parameterized Looped Schedules

Ed F. Deprettere, Shuvra S. Bhattacharyya, Claudiu Zissulescu, 2006 .

Quantization using wavelet based temporal decomposition of the LSF

Ed F. Deprettere, W. Bastiaan Kleijn, Aweke N. Lemma, 1997, EUROSPEECH.

Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations

Keshab K. Parhi, Ed F. Deprettere, Jun Ma, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Translating affine nested-loop programs to process networks

Alexandru Turjan, Ed F. Deprettere, Bart Kienhuis, 2004, CASES '04.

Analysis of ESPRIT based joint angle-frequency estimation

Ed F. Deprettere, Alle-Jan van der Veen, Aweke N. Lemma, 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).

Parallel architecture for a pel-recursive motion estimation algorithm

Ed F. Deprettere, E. D. Frimout, J. N. Driessen, 1992, [1992] Proceedings of the International Conference on Application Specific Array Processors.

A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures

Ed F. Deprettere, Erwin A. de Kock, Bart Kienhuis, 1999, J. VLSI Signal Process..

A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms

Keshab K. Parhi, Ed F. Deprettere, Jun Ma, 2001, IEEE Trans. Signal Process..

USHA: Unified software and hardware architecture for video decoding

Ed F. Deprettere, S. K. Nandy, Hristo Nikolov, 2011, 2011 IEEE 9th Symposium on Application Specific Processors (SASP).

Context-aware process networks

Ed F. Deprettere, Henk J. Sips, Hylke W. van Dijk, 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

Introduction

Ed F. Deprettere, 1991, J. VLSI Signal Process..

Realizations of the Extended Linearization Model

Alexandru Turjan, Ed F. Deprettere, Bart Kienhuis, 2002 .

A class of analysis-by-synthesis predictive coders for high quality speech coding at rates between 4.8 and 16 kbit/s

Ed F. Deprettere, Peter Kroon, 1988, IEEE J. Sel. Areas Commun..

Stable construction of multiscale fuzzy-wavelet system for image recovery and compression

Ed F. Deprettere, Yi Yu, Shaohua Tan, 1996, Optics & Photonics.

Efficient modeling of interconnections in a VLSI circuit

Ed F. Deprettere, Patrick Dewilde, H. Nelis, 1989, IEEE International Symposium on Circuits and Systems,.

Hierarchical run time deadlock detection in process networks

Bin Jiang, Ed F. Deprettere, Bart Kienhuis, 2008, 2008 IEEE Workshop on Signal Processing Systems.

Numerically stable Jacobi array for parallel singular value decomposition (SVD) updating

Ed F. Deprettere, Marc Moonen, F Vanpoucke, 1994, Optics & Photonics.

Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study

Ed F. Deprettere, Andy D. Pimentel, Todor Stefanov, 2008, SAMOS.

Guest Editor's Introduction

Ed F. Deprettere, Jeong-A Lee, Gerben J. Hekstra, 2000, J. VLSI Signal Process..

Design and VLSI implementation of a concurrent solver for N coupled least-squares fitting problems

Ed F. Deprettere, K. Jainandunsing, 1985, ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing.

Space Partitioning for Mapping Radiosity Computations onto a Pipelined Parallel Architecture (II)

Ed F. Deprettere, Li-Sheng Shen, F. A. J. Laarakker, 1991, Advances in Computer Graphics Hardware.

A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks

Alexandru Turjan, Ed F. Deprettere, Bart Kienhuis, 2002, ASAP.

Systolic array implementation of nested loop programs

Ed F. Deprettere, Lothar Thiele, J. Bu, 1990, [1990] Proceedings of the International Conference on Application Specific Array Processors.

Fast non-stationary lattice recursions for adaptive modeling and estimation

Ed F. Deprettere, 1982, ICASSP.

Transforming Signal Processing Applications into Parallel Implementations

Ed F. Deprettere, Erwin A. de Kock, Ingrid Verbauwhede, 2007, EURASIP J. Adv. Signal Process..

Engineering multirate convolutions for radar imaging

Ed F. Deprettere, Laurens Bierens, 1996, 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing Conference Proceedings.

On the localization problem in systolic algorithm design

Ed F. Deprettere, J. Bu, 1989, IEEE International Symposium on Circuits and Systems,.

The design of a 50 Mflop arithmetic chip for massively parallel pipelined DSP algorithms: the floating point pipeline CORDIC processor

Ed F. Deprettere, Patrick Dewilde, A. J. van der Hoeven, 1989 .

Editorial: Transforming Signal Processing Applications into Parallel Implementations

Roger Woods, Ed F. Deprettere, Ingrid Verbauwhede, 2007 .

Multi-scale non-linear modelling using wavelet networks

Ed F. Deprettere, Aweke N. Lemma, 1996 .

Classifying interprocess communication in process network representation of nested-loop programs

Alexandru Turjan, Ed F. Deprettere, Bart Kienhuis, 2007, TECS.

Processor clustering for the design of optimal fixed-size systolic arrays

Ed F. Deprettere, Jichun Bu, E. Deprettere, 1991, Proceedings of the International Conference on Application Specific Array Processors.

Example of combined algorithm development and architecture design

Ed F. Deprettere, 1993, Integr..

Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell

Ed F. Deprettere, Todor Stefanov, Sjoerd Meijer, 2009, SAMOS.

Communication synthesis in a multiprocessor environment

Ed F. Deprettere, Bart Kienhuis, Claudiu Zissulescu, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Multiport memory and floating point Cordic pipeline in Jacobium processing elements

Ed F. Deprettere, A. Looye, G. Hekstra, 1998, 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374).

Parallel VLSI matrix pencil algorithm for high resolution direction finding

Ed F. Deprettere, Alle-Jan van der Veen, 1991, IEEE Trans. Signal Process..

Compilation From Matlab to Process Networks Realized in FPGA

Ed F. Deprettere, Bart Kienhuis, Richard L. Walke, 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).

Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems

Ed F. Deprettere, Todor Stefanov, 2010, SCOPES 2010.

Unifying parametrized VLSI Jacobi algorithms and architectures

Ed F. Deprettere, Marc Moonen, 1993, Optics & Photonics.

Handbook of Signal Processing Systems

Rainer Leupers, Ed F. Deprettere, Shuvra S. Bhattacharyya, 2010 .

Parallel and adaptive high-resolution direction finding

Ed F. Deprettere, Marc Moonen, Filiep Vanpoucke, 1994, IEEE Trans. Signal Process..

Analysis of joint angle-frequency estimation using ESPRIT

Ed F. Deprettere, Alle-Jan van der Veen, Aweke N. Lemma, 2003, IEEE Trans. Signal Process..

Efficient implementations of pipelined CORDIC-based IIR digital filters using fast orthonormal μ-rotations

Keshab K. Parhi, Ed F. Deprettere, Gerben J. Hekstra, 1998, Optics & Photonics.

An Integer Linear Programming Approach to Classify the Communication in Process Networks

Alexandru Turjan, Ed F. Deprettere, Bart Kienhuis, 2004, SCOPES.

A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix

Ed F. Deprettere, Paul F. C. Krekel, 1989, J. VLSI Signal Process..

A hardware design system based on object-oriented principles

Ed F. Deprettere, Patrick Dewilde, A. J. van der Hoeven, 1991, Proceedings of the European Conference on Design Automation..

Converting weakly dynamic programs to equivalent process network specifications

Ed F. Deprettere, Todor Stefanov, 2000 .

Fast rotations: low-cost arithmetic methods for orthonormal rotation

Ed F. Deprettere, Gerben J. Hekstra, 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

HIFI: From Parallel Algorithm to Fixed-Size VLSI Processor Array

Ed F. Deprettere, Paul Wielage, Patrick Dewilde, 1993 .

A New Space Partitioning for Mapping Computations of the Radiosity Method onto a Highly Pipelined Parallel Architecture

Ed F. Deprettere, Li-Sheng Shen, Patrick Dewilde, 1990, Advances in Computer Graphics Hardware V.

Hardware Implementation of the First Stage of the Blast Algorithms

Ed F. Deprettere, Bart Kienhuis, Herman P. Spaink, 2003 .

Hifi: an environment for the high level description and analysis of VLSI networks

Ed F. Deprettere, Patrick Dewilde, A. J. van der Hoeven, 1989 .

Parallel architecture for a pel-recursive motion estimation algorithm

Ed F. Deprettere, Emmanuel D. Frimout, Johannes N. Driessen, 1992, CompEuro 1992 Proceedings Computer Systems and Software Engineering.

MODEL AND METHODS FOR REGULAR ARRAY DESIGN

Ed F. Deprettere, Paul Wielage, Peter Held, 1993 .

Dynamic Dataflow Graphs

Ed F. Deprettere, Shuvra S. Bhattacharyya, Bart D. Theelen, 2018, Handbook of Signal Processing Systems.

Efficient External Memory Interface for Multi-Processor Platforms Realized on FPGA Chips

Ed F. Deprettere, Todor Stefanov, Hristo Nikolov, 2007, 2007 International Conference on Field Programmable Logic and Applications.

A design system for massively parallel hardware

Ed F. Deprettere, Paul Wielage, Patrick Dewilde, 1994 .

The 10 years of SAMOS

Ed F. Deprettere, Shuvra S. Bhattacharyya, Andy D. Pimentel, 2010 .

Modeling Stream-Based Applications Using the SBF Model of Computation

Ed F. Deprettere, Bart Kienhuis, B. Kienhuis, 2001, J. VLSI Signal Process..

Automated Synthesis of Hardware Process Networks from Sequential C Code

Ed F. Deprettere, Hristo Nikolov, Vinod Kathail, 2008 .

Regular-pulse excitation-A novel approach to effective and efficient multipulse coding of speech

Ed F. Deprettere, Peter Kroon, Robert J. Sluyter, 1986, IEEE Trans. Acoust. Speech Signal Process..

Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration

Ed F. Deprettere, Laurentiu Nicolae, E. Deprettere, 2004, SAMOS.

Expression synthesis in process networks generated by LAURA

Ed F. Deprettere, Bart Kienhuis, Claudiu Zissulescu, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

The construction of a retargetable simulator for an architecture template

Ed F. Deprettere, Bart Kienhuis, Pieter van der Wolf, 1998, CODES.

Generalized orthogonal filters for stochastic prediction and modelling

Ed F. Deprettere, Patrick Dewilde, 1980 .

Design and implementation of a floating-point quasi-systolic general purpose CORDIC rotator for high-rate parallel data and signal processing

Ed F. Deprettere, A. A. de Lange, E. Deprettere, 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

Modeling and FPGA implementation of applications using parameterized process networks with non-static parameters

Ed F. Deprettere, Todor Stefanov, Hristo Nikolov, 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

Deriving process networks from weakly dynamic applications in system-level design

Ed F. Deprettere, Todor Stefanov, E. Deprettere, 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).

Direction finding of multiple wide-band emitters using state-space modeling

Ed F. Deprettere, Marc Moonen, Filiep Vanpoucke, 1994, Signal Process..

Solving Out-of-Order Communication in Kahn Process Networks

Alexandru Turjan, Ed F. Deprettere, Bart Kienhuis, 2002, J. VLSI Signal Process..

A 'Jacobi' signal processing unit for time-adaptive SVD

Ed F. Deprettere, Gerben J. Hekstra, Hylke W. van Dijk, 1994, Proceedings of ICASSP '94. IEEE International Conference on Acoustics, Speech and Signal Processing.

A New Model for the High Level Description and Simulation of VLSI Networks

Ed F. Deprettere, Patrick Dewilde, A. J. van der Hoeven, 1989, 26th ACM/IEEE Design Automation Conference.

A trace transformation technique for communication refinement

Ed F. Deprettere, Pieter van der Wolf, Paul Lieverse, 2001, CODES '01.

Multiresolution ESPRIT algorithm

Ed F. Deprettere, Alle-Jan van der Veen, Aweke N. Lemma, 1999, IEEE Trans. Signal Process..

Compaan: deriving process networks from Matlab for embedded signal processing architectures

Ed F. Deprettere, Bart Kienhuis, Edwin Rijpkema, 2000, CODES '00.

A parallel system for photo realistic artificial scene rendering

Ed F. Deprettere, Jichun Bu, G. Boersma, 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications

Ed F. Deprettere, Jérôme Lemaitre, 2006, Euro-Par.

Joint angle-frequency estimation using multi-resolution ESPRIT

Ed F. Deprettere, Alle-Jan van der Veen, Aweke N. Lemma, 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

Increasing Pipelined IP Core Utilization in Process Networks Using Exploration

Ed F. Deprettere, Bart Kienhuis, Claudiu Zissulescu, 2004, FPL.

Efficient orthogonal realization of image transforms

Ed F. Deprettere, Richard Heusdens, Gerben J. Hekstra, 1996, Optics & Photonics.

Parallel and adaptive high-resolution direction finding

Ed F. Deprettere, Marc Moonen, F Vanpoucke, 1992, Optics & Photonics.

Requirements for Interfacing IP-Components in Re-configurable Platforms

Ed F. Deprettere, Sylvain Alliot, Jérôme Lemaitre, 2006, J. VLSI Signal Process..

State space behavior in time-varying biorthogonal filter banks

Ed F. Deprettere, Aweke N. Lemma, 1996, 1996 8th European Signal Processing Conference (EUSIPCO 1996).

Detection and blanking of GSM signals in radio-astronomical observations

Ed F. Deprettere, Amir Leshem, A.-J. van der Veen, 1999, SPAWC 1999.

A hierarchical classification scheme to derive interprocess communication in process networks

Alexandru Turjan, Ed F. Deprettere, Bart Kienhuis, 2004, Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004..

Converting sequential iterative algorithms to recurrent equations for automatic design of systolic arrays

Ed F. Deprettere, J. Bu, 1988, ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing.

A hierarchical classification scheme to derive interprocess communication in process networks

Alexandru Turjan, Ed F. Deprettere, Bart Kienhuis, 2004 .

Design and VLSI Implementation of a Concurrent Solver for N-Coupled Least-Squares Fitting Problems

Ed F. Deprettere, K. Jainandunsing, 1986, IEEE J. Sel. Areas Commun..

Pipelined cordic architectures for fast VLSI filtering and array processing

Ed F. Deprettere, Patrick Dewilde, R. Udo, 1984, ICASSP.

Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures

Heinrich Meyr, Ed F. Deprettere, Jan M. Rabaey, 1994, ISCAS.

Waveform interpolation coding with pitch-spaced subbands

Ed F. Deprettere, Huimin Yang, W. Bastiaan Kleijn, 1998, ICSLP.