T. Sugibayashi

发表

50×20 crossbar switch block (CSB) with two-varistors (a-Si/SiN/a-Si) selected complementary atom switch for a highly-dense reconfigurable logic

T. Sakamoto, N. Iguchi, N. Banno, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy

N. Banno, T. Sugibayashi, X. Bai, 2020, 2020 IEEE Symposium on VLSI Technology.

Hierarchical Word-Line Architecture for Large Capacity DRAMs

T. Sugibayashi, T. Morotani, M. Takada, 1997 .

A 250-MHz 1-Mbit embedded MRAM macro using 2T1MTJ cell with bitline separation and half-pitch shift architecture

N. Kasai, N. Sakimura, H. Honjo, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

High-Density and Fault-Tolerant Cu Atom Switch Technology Toward 28nm-node Nonvolatile Programmable Logic

N. Banno, M. Tada, H. Hada, 2018, 2018 IEEE Symposium on VLSI Technology.

MRAM Cell Technology for Over 500-MHz SoC

N. Sakimura, H. Honjo, S. Saito, 2007, IEEE Journal of Solid-State Circuits.

A 16-Mb Toggle MRAM With Burst Modes

N. Kasai, N. Sakimura, K. Mori, 2007, IEEE Journal of Solid-State Circuits.

Fabrication of a 99%-energy-less nonvolatile multi-functional CAM chip using hierarchical power gating for a massively-parallel full-text-search engine

T. Endoh, S. Fukami, S. Ikeda, 2013, 2013 Symposium on VLSI Technology.

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor

I. Naritake, T. Murotani, T. Okuda, 1999, IEEE Journal of Solid-State Circuits.

A distributive serial multi-bit parallel test scheme for large capacity DRAMs

I. Naritake, T. Sugibayashi, T. Takeshima, 1993, Symposium 1993 on VLSI Circuits.

MRAM Cell Technology for Over 500MHz SoC

N. Sakimura, H. Honjo, S. Saito, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

A content addressable memory using magnetic domain wall motion cells

T. Endoh, S. Fukami, N. Kasai, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A 512kb cross-point cell MRAM

N. Sakimura, S. Miura, S. Tahara, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

T. Endoh, T. Ohsawa, H. Koike, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme

N. Kasai, N. Sakimura, T. Sugibayashi, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

A 500-MHz MRAM macro for high-performance SoCs

N. Sakimura, H. Honjo, S. Saito, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current

N. Sakimura, S. Miura, S. Tahara, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Spintronics primitive gate with high error correction efficiency 6(Perror)2 for logic-in memory architecture

T. Endoh, S. Fukami, N. Kasai, 2012, 2012 Symposium on VLSI Technology (VLSIT).

20-nm magnetic domain wall motion memory with ultralow-power operation

S. Fukami, S. Ikeda, N. Kasai, 2013, 2013 IEEE International Electron Devices Meeting.

High-speed and reliable domain wall motion device: Material design for embedded memory and logic application

S. Fukami, S. Ikeda, N. Kasai, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Robust Cu atom switch with over-400°C thermally tolerant polymer-solid electrolyte (TT-PSE) for nonvolatile programmable logic

N. Banno, M. Tada, T. Sakamoto, 2016, 2016 IEEE Symposium on VLSI Technology.

Toggling cell with four antiferromagnetically coupled ferromagnetic layers for high density MRAM with low switching current

S. Miura, S. Tahara, Y. Asao, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A low-power Cu atom switch programmable logic fabricated in a 40nm-node CMOS technology

N. Banno, M. Tada, T. Sakamoto, 2017, 2017 Symposium on VLSI Technology.

A 30 ns 256 Mb DRAM with multi-divided array structure

T. Matano, N. Kasai, M. Fujita, 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 12 ns 8 MB DRAM secondary cache for a 64 b microprocessor

I. Naritake, M. Togo, T. Sugibayashi, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A novel two-varistors (a-Si/SiN/a-Si) selected complementary atom switch (2V-1CAS) for nonvolatile crossbar switch with multiple fan-outs

N. Banno, M. Tada, T. Sakamoto, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

A 1 Gb DRAM for file applications

I. Naritake, T. Murotani, T. Sugibayashi, 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

A 16Mb toggle MRAM with burst modes

S. Fukami, N. Kasai, N. Sakimura, 2006, 2006 IEEE Asian Solid-State Circuits Conference.