C. C. Jong

Expandable Library of Customized Functional Modules For Digital ASIC Design

L. S. Ng, C. C. Jong, G. N. Toh, 1994 .

A lower bound on general minimal resource interval scheduling with arbitrary component selection

C. C. Jong, Z. X. Shen, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Using time zones for data path allocation in high-level synthesis of digital systems

Y. Y. H. Lam, C. C. Jong, C. Jong, 1995 .

FPGA implementation of a digital IQ demodulator using VHDL

Y. Y. H. Lam, C. C. Jong, L. S. Ng, 1997, FPL.

Scalable linear array architectures for matrix inversion using Bi-z CORDIC

C. C. Jong, J. W. Luo, C. Jong, 2012, Microelectron. J..

Rule-Based Processing of IC Layout Extracted From Chip Image

L. S. Ng, C. C. Jong, O. K. Tan, 1994 .

Low Level Representation of VHDL Behavioural Description for Synthesis of Digital ASICs

C. C. Jong, K. H. Chan, T. K. Ang, 1993 .

Time-zone: a new algorithm for register allocation in data path synthesis

Y. Y. H. Lam, C. C. Jong, S. S. Lim, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Implementation of synthesized digital systems with VHDL

L. S. Ng, C. C. Jong, 1995, 1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings.

On fast exploration of ASIC design space

C. C. Jong, Z. X. Shen, 1996, 2nd International Conference on ASIC.

Automatic Generation of Data Flow Graphs For Testing of High-Level Synthesis Algorithms

Liter Siek, C. C. Jong, W. Lau, 1995 .