M. Irwin

发表

Thermal neutron induced soft error rate measurement in semiconductor memories and circuits

R. Rajaraman, V. Narayanan, C. Celik, 2008 .

TESTING NEUTRON-INDUCED SOFT ERRORS IN SEMICONDUCTOR MEMORIES Participants:

N. Vijaykrishnan, K. Ünlü, M. Irwin, 2007 .

- Compiler-Directed Communication Energy Optimizations for Microsensor Networks

Narayanan Vijaykrishnan, Mary Jane Irwin, Alok Choudhary, 2012 .

Adaptive error protection for energy efficiency

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

Distributed Fault Diagnosis in the Butterfly Parallel Processor

Chita R. Das, Mary Jane Irwin, Woei Lin, 1989, ICPP.

Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnect

Mahmut T. Kandemir, Mary Jane Irwin, Wei Ding, 2013, PACT 2013.

Power-Aware Designers at Odds with Power Grid Designers?

Mary Jane Irwin, M. J. Irwin, M. Irwin, 2003, IEEE Des. Test Comput..

Special Issue Short Papers Transistor Sizing for Low Power CMOS Circuits

Mary Jane Irwin, Robert Michael Owens, M. Borah, 1996 .

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001

Mary Jane Irwin, Enrico Macii, Vivek De, 2001, International Symposium on Low Power Electronics and Design.

Energy characterization based on clustering

M. J. Irwin, R. Owens, M. Irwin, 1996, 33rd Design Automation Conference Proceedings, 1996.

Tota I Power 0 pt i m izat i o n t h rough Si mu Ita neous I y Multiple-V,, Multiple-V,, Assignment and Device Sizing with Stack Forcing

Mary Jane Irwin, Mahmut Kandemir, Narayanan Vijaykrishnan, 2004 .

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Mary Jane Irwin, M. Irwin, 1999, DAC 1999.

Memory energy characterization and optimization for the SPEC2000 benchmarks

M. Kandemir, A. Sivasubramaniam, N. Vijaykrishnan, 2001, Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization. WWC-4 (Cat. No.01EX538).

Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2009, Washington, DC, USA, March 7-11, 2009

Mary Jane Irwin, Mary Lou Soffa, M. Soffa, 2009, ASPLOS.

Energy Behavior of Java Applications from the Memory Perspective

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, Java Virtual Machine Research and Technology Symposium.

Compiler-guided leakage optimization for banked scratch-pad memories

Mahmut T. Kandemir, Mary Jane Irwin, Guangyu Chen, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Small signal model for low power DSP

Mary Jane Irwin, Robert Michael Owens, H. Mehta, 1995, 1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers.

Motion Analysis on the Micro Grained Array Processor

Mary Jane Irwin, Robert Michael Owens, Heung-Nam Kim, 1997, Real Time Imaging.

MGAP applications in machine perception

Mary Jane Irwin, Robert Michael Owens, Heung-Nam Kim, 1995, Proceedings of Conference on Computer Architectures for Machine Perception.

Digit pipelined processors

Mary Jane Irwin, Robert Michael Owens, R. Owens, 1987, The Journal of Supercomputing.

The MGAP-2: an advanced, massively parallel VLSI signal processor

Mary Jane Irwin, Robert Michael Owens, Thomas P. Kelliher, 1995, 1995 International Conference on Acoustics, Speech, and Signal Processing.

2-D discrete cosine transforms on a fine grain array processor

Mary Jane Irwin, Robert Michael Owens, M. Borah, 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

A rational arithmetic processor

Mary Jane Irwin, Dwight R. Smith, M. Irwin, 1981, 1981 IEEE 5th Symposium on Computer Arithmetic (ARITH).

Recent developments in performance driven Steiner routing: an overview

Mary Jane Irwin, Robert Michael Owens, Manjit Borah, 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

A module generator for high performance CMOS circuits

Mary Jane Irwin, Robert Michael Owens, M. J. Irwin, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

An Efficient Systolic Architecture For Qmf Filter Bank Trees

Mary Jane Irwin, Robert Michael Owens, M. Visllwanatb, 1992, Workshop on VLSI Signal Processing.

A digit pipelined dynamic time warp processor [word recognition]

Mary Jane Irwin, M. J. Irwin, M. Irwin, 1988, IEEE Trans. Acoust. Speech Signal Process..

PERFLEX: a performance driven module generator

Mary Jane Irwin, Robert Michael Owens, Soohong Kim, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

A unified energy framework with integrated hardware-software optimizations

Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut Kandemir, 2000, International Symposium on Computer Architecture.

Design of a nanosensor array architecture

Narayanan Vijaykrishnan, Mary Jane Irwin, Wei Xu, 2004, GLSVLSI '04.

Energy-driven integrated hardware-software optimizations using SimplePower

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

Energy-performance trade-offs for spatial access methods on memory-resident data

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, The VLDB Journal.

Multi-way FSM decomposition based on interconnect complexity

Mary Jane Irwin, Robert Michael Owens, Wen-Lin Yang, 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

Leakage Current: Moore's Law Meets Static Power

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, Computer.

Link Shutdown Opportunities During Collective Communications in 3-D Torus Nets

Mary Jane Irwin, Sayaka Akioka, Padma Raghavan, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

An edge-based heuristic for Steiner routing

Mary Jane Irwin, Robert Michael Owens, Manjit Borah, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

ECube: An Efficient Architecture for Analyzing Time-Varying Spectra

Mary Jane Irwin, Robert Michael Owens, Mohan Vishwanath, 1992, The Fifth International Conference on VLSI Design.

The Arithmetic Cube: error analysis and simulation

Mary Jane Irwin, Robert Michael Owens, M. Vishwanath, 1991, Proceedings of the International Conference on Application Specific Array Processors.

The arithmetic cube II: a second generation VLSI DSP processor

Mary Jane Irwin, Robert Michael Owens, M. Vishwanath, 1991, [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing.

Being Stingy with Multipliers

Mary Jane Irwin, Robert Michael Owens, M. J. Irwin, 1990, IEEE Trans. Computers.

Implementing algorithms for convolution on arrays of adders

Mary Jane Irwin, Robert Michael Owens, R. Owens, 1989, International Conference on Acoustics, Speech, and Signal Processing,.

Multidimensional algorithms for VLSI processors

Mary Jane Irwin, Robert Michael Owens, R. Owens, 1988, ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing.

The Arithmetic Cube

Mary Jane Irwin, Robert Michael Owens, R. Owens, 1987, IEEE Transactions on Computers.

A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors

Mary Jane Irwin, Robert Michael Owens, R. Owens, 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Parallel uses for serial arithmetic in signal processors

Mary Jane Irwin, Robert Michael Owens, R. Owens, 1991, Optics & Photonics.

DECOMPOSER: a synthesizer for systolic systems

Mary Jane Irwin, Robert Michael Owens, Pao-Po Hou, 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

A high level synthesis tool for systolic designs

Mary Jane Irwin, Robert Michael Owens, Pao-Po Hou, 1988, [1988] Proceedings. International Conference on Systolic Arrays.

Optimizing sensor movement planning for energy efficiency

Mary Jane Irwin, Thomas F. La Porta, Piotr Berman, 2005, ISLPED '05.

Optimizing sensor movement planning for energy efficiency

Mary Jane Irwin, Thomas F. La Porta, Piotr Berman, 2011, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

A compiler-based approach for dynamically managing scratch-pad memories in embedded systems

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Three dimensional graphics algorithms on the Micro-Grain Array Processor. II

Benjamin Bishop, Mary Jane Irwin, Robert Michael Owens, 1997, Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97.

VLSI architectures for the discrete wavelet transform

Mary Jane Irwin, Robert Michael Owens, M. Vishwanath, 1995 .

Area-time-power tradeoffs in parallel adders

Mary Jane Irwin, Robert Michael Owens, M. J. Irwin, 1996 .

Transistor sizing for low power CMOS circuits

Mary Jane Irwin, Robert Michael Owens, Manjit Borah, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Power-delay characteristics of CMOS adders

Mary Jane Irwin, Robert Michael Owens, Chetana N. Keltcher, 1994, IEEE Trans. Very Large Scale Integr. Syst..

Influence of array allocation mechanisms on memory system energy

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001.

Reliability-aware Co-synthesis for Embedded Systems

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004..

Tuning garbage collection for reducing memory system energy in an embedded java environment

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, TECS.

Studying energy trade offs in offloading computation/compilation in Java-enabled mobile devices

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, IEEE Transactions on Parallel and Distributed Systems.

Energy-aware compilation and execution in Java-enabled mobile devices

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2003, Proceedings International Parallel and Distributed Processing Symposium.

Soft error and energy consumption interactions: a data cache perspective

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

Soft errors issues in low-power caches

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Plagiarism on the rise

Mary Jane Irwin, Ronald F. Boisvert, M. Irwin, 2006, CACM.

Improving soft-error tolerance of FPGA configuration bits

M. Kandemir, Yuan Xie, N. Vijaykrishnan, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Load Miss Prediction - Exploiting Power Performance Trade-offs

Mary Jane Irwin, Padma Raghavan, Konrad Malkowski, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

Conjugate gradient sparse solvers: performance-power characteristics

Mary Jane Irwin, Ingyu Lee, Padma Raghavan, 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

Efficiently computing communication complexity for multilevel logic synthesis

Mary Jane Irwin, Robert Michael Owens, TingTing Hwang, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Neutron-induced soft error rate measurements in semiconductor memories

Mary Jane Irwin, Kenan Unlu, Sacit M. Cetiner, 2007 .

Testing Neutron-induced Soft Errors

N. Vijaykrishnan, M. Irwin, R. Krishnan, 2007 .

Analyzing heap error behavior in embedded JVM environments

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..

Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuan Xie, 2009, 2009 IEEE/ACM International Symposium on Nanoscale Architectures.

Estimating influence of data layout optimizations on SDRAM energy consumption

M. Kandemir, F. Catthoor, N. Vijaykrishnan, 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

Optimising power efficiency in trace cache fetch unit

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2007, IET Comput. Digit. Tech..

Evaluating run-time techniques for leakage power reduction

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuh-Fang Tsai, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Reducing leakage energy in FPGAs using region-constrained placement

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2004, FPGA '04.

ChipPower: an architecture-level leakage simulator

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2004, IEEE International SOC Conference, 2004. Proceedings..

Some issues in gray code addressing

Mary Jane Irwin, Robert Michael Owens, Huzefa Mehta, 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

Techniques for low energy software

Mary Jane Irwin, Robert Michael Owens, Huzefa Mehta, 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

Priority Scheduling in Digital Microfluidics-Based Biochips

Narayanan Vijaykrishnan, Mary Jane Irwin, Kevin M. Irick, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs

Narayanan Vijaykrishnan, Mary Jane Irwin, Soumya Eachempati, 2011 .

An Exploration of Hardware Architectures for Face Detection

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2006 .

Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip

Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides, 2005, Adv. Comput..

Dynamic management of scratch-pad memory space

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

A case for digit serial VLSI signal processors

Mary Jane Irwin, Robert Michael Owens, R. Owens, 1990, J. VLSI Signal Process..

A comparison of two digit serial VLSI adders

Mary Jane Irwin, Robert Michael Owens, R. Owens, 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

An Overview of the Penn State Design System

Mary Jane Irwin, Robert Michael Owens, R. Owens, 1987, 24th ACM/IEEE Design Automation Conference.

Characterization and modeling of run-time techniques for leakage power reduction

Narayanan Vijaykrishnan, Mary Jane Irwin, Yuh-Fang Tsai, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Image processing with the MGAP: a cost effective solution

Mary Jane Irwin, Robert Michael Owens, Raminder Singh Bajwa, 1993, [1993] Proceedings Seventh International Parallel Processing Symposium.

An integer linear programming-based tool for wireless sensor networks

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2005, J. Parallel Distributed Comput..

Process-Variation-Aware Adaptive Cache Architecture and Management

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2009, IEEE Transactions on Computers.

Core vs. uncore: The heart of darkness

Mary Jane Irwin, Yuan Xie, Jishen Zhao, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Leakage energy management in cache hierarchies

Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.