蔡懿慈

发表

Fast Synthesis of Low Power Clock Trees Based on Register Clustering

邓超, 周强, 蔡懿慈, 2015 .

Wire-length Driven Legalization Algorithm for Large-scale ASIC

周强, 高文超, 蔡懿慈, 2013 .

Partition-Based Global Placement Considering Wire-Density Uniformity for CMP Variations

周强, 蔡懿慈, 董昌道, 2011 .

Shielding Area Optimization Under the Solution of Interconnect Crosstalk

赵鑫, 周强, 蔡懿慈, 2005 .

Register Clustering Methodology for Low Power Clock Tree Synthesis

邓超, 周强, 蔡懿慈, 2015 .

Three-dimensional chip heat through-hole and blank space redistributing method with optimized performance

蔡懿慈, 洪先龙, 马昱春, 2008 .

A multi—step standard—cell placement algorithm of optimizing timing and congestion behavior

吴为民, 蔡懿慈, 洪先龙, 2002 .

Incremental Placement-Based Clock Network Minimization Methodology

黄亮, 周强, 蔡懿慈, 2008 .

An Efficient Buffer Sizing Algorithm for Clock TreesConsidering Process Variations

邓超, 周强, 蔡懿慈, 2015 .

A Selected InversionApproach for Locality Driven Vectorless Power Grid Verification.

赵威, 周强, 蔡懿慈, 2015 .

Satisfiability problem-based manufacturable hot spot disconnecting and rerouting method

杨帆, 周强, 蔡懿慈, 2010 .

Quick method for implementing noise optimization of integrated circuit supply network using decoupling capacitor

蔡懿慈, 洪先龙, 谭向东, 2003 .

Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths

周强, 蔡懿慈, 祁仲冬, 2015 .

A Yield-Driven Gridless Router

周强, 蔡懿慈, 洪先龙, 2007 .

PhyD-XML：VLSI物理设计数据标记语言设计与实现

周强, 蔡懿慈, 洪先龙, 2003 .

Priority-Based Routing Resource Assignment Considering Crosstalk

刘斌, 熊焰, 周强, 2006 .

Congestion-Driven Multilevel Full-Chip Routing Framework

姚海龙, 蔡懿慈, 洪先龙, 2008 .

Flexibility in Rectilinear Steiner Minimal Tree

马坤, 周强, 蔡懿慈, 2014 .