Hamid Mahmoodi

发表

Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologies

Anuj Pushkarna, Sajna Raghavan, Hamid Mahmoodi, 2010, 23rd IEEE International SOC Conference.

Comparative analysis of copper and CNT interconnects for H-tree clock distribution

Hamid Mahmoodi, Vish Ganti, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS

Hamid Mahmoodi, Rajani Kuchipudi, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Low-overhead design technique for calibration of maximum frequency at multiple operating points

Swarup Bhunia, Hamid Mahmoodi, Somnath Paul, 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

Robust FinFET SRAM design based on dynamic back-gate voltage adjustment

Behzad Ebrahimi, Ali Afzali-Kusha, Hamid Mahmoodi, 2014, Microelectron. Reliab..

Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies

Hamid Mahmoodi, Joyce Yeung, 2006, 2006 IEEE International SOC Conference.

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2008, J. Electron. Test..

Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, 14th Asian Test Symposium (ATS'05).

Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering

Kaushik Roy, Hunsoo Choo, Hamid Mahmoodi, 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

Flip-flop design using novel pulse generation technique

Farshad Moradi, Hamid Mahmoodi, Jens Kargaard Madsen, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Document Clustering Based On Semi-Supervised Term Clustering

Hamid Mahmoodi, Eghbal G. Mansoori, 2012 .

Pre-capturing static pulsed flip-flops

Hamid Mahmoodi, Aliakbar Ghadiri, H. Mahmoodi, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging

Houman Homayoun, Hamid Mahmoodi, Hassan Salmani, 2016, Microelectron. Reliab..

Energy-Efficient Ternary Multipliers Using CNT Transistors

Fazel Sharifi, Sepehr Tabrizchi, Abdel-Hameed A. Badawy, 2020, Electronics.

Leakage Current in Deep-Submicron CMOS Circuits

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2002, J. Circuits Syst. Comput..

A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, Design, Automation and Test in Europe.

Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates

Houman Homayoun, Hamid Mahmoodi, Hassan Salmani, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

High performance and low power FIR filter design based on sharing multiplication

Kaushik Roy, Hunsoo Choo, Hamid Mahmoodi, 2002, ISLPED '02.

Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design

Houman Homayoun, Hamid Mahmoodi, Adarsh Reddy Ashammagari, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Clock Gating and Negative Edge Triggering for Energy Recovery Clock

Hamid Mahmoodi, Vishwanadh Tirumalashetty, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Read static noise margin aging model considering SBD and BTI effects for FinFET SRAMs

Behzad Ebrahimi, Ali Afzali-Kusha, Hamid Mahmoodi, 2016, Microelectron. Reliab..

Thermal estimation for accurate estimation of impact of BTI aging effects on nano-scale SRAM circuits

Hamid Mahmoodi, Ankitchandra Shah, 2010, 23rd IEEE International SOC Conference.

65NM sub-threshold 11T-SRAM for ultra low voltage applications

Farshad Moradi, Hamid Mahmoodi, Snorre Aunet, 2008, 2008 IEEE International SOC Conference.

Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS

Anuj Pushkarna, Hamid Mahmoodi, 2010, GLSVLSI '10.

Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology

Kaushik Roy, Farshad Moradi, Hamid Mahmoodi, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS

Reza Lotfi, Hamid Mahmoodi, Khalil Mafinezhad, 2011, IEICE Electron. Express.

First level hold: a novel low-overhead delay fault testing technique

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2004 .

Energy recovery clocked dynamic logic

Kaushik Roy, Hamid Mahmoodi, Matthew Cooke, 2005, GLSVLSI '05.

Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection

Swarup Bhunia, Hamid Mahmoodi, Somnath Paul, 2010, TODE.

Novel low-overhead operand isolation techniques for low-power datapath synthesis

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, 2005 International Conference on Computer Design.

Postsilicon Adaptation for Low-Power SRAM under Process Variation

Marilyn Wolf, Jason Schlessman, Hamid Mahmoodi, 2010, IEEE Design & Test of Computers.

Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, IEEE International Conference on Test, 2005..

Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability

Kaushik Roy, Ashish Goel, Swarup Bhunia, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Low Power Synthesis of Dynamic Logic Circuits Using Fine-Grained Clock Gating

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2006, Proceedings of the Design Automation & Test in Europe Conference.

A novel synthesis approach for active leakage power reduction using dynamic supply gating

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, Proceedings. 42nd Design Automation Conference, 2005..

A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Spin-Based Imprecise 4-2 Compressor for Energy-Efficient Multipliers

Keivan Navi, Fazel Sharifi, Hamid Mahmoodi, 2019 .

Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Full-custom design project for digital VLSI and IC design courses using synopsys generic 90nm CMOS library

Vazgen Melikyan, Hamid Mahmoodi, Richard Goldman, 2009, 2009 IEEE International Conference on Microelectronic Systems Education.

Statistical design and optimization of SRAM cell for yield enhancement

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2004, ICCAD 2004.

New subthreshold concepts in 65nm CMOS technology

Farshad Moradi, Ali Peiravi, Hamid Mahmoodi, 2009, 2009 10th International Symposium on Quality Electronic Design.

Improved write margin 6T-SRAM for low supply voltage applications

Farshad Moradi, Hamid Mahmoodi, Tuan Vu Cao, 2009, 2009 IEEE International SOC Conference (SOCC).

Session 8 - Characterization and test methods for device variability in nanoscale technologies

Hamid Mahmoodi, Jeanne Trinko Mechler, 2008, CICC.

A novel low-power scan design technique using supply gating

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

First level hold: a novel low-overhead delay fault testing technique

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS

Reza Lotfi, Hamid Mahmoodi, Khalil Mafinezhad, 2012, Microelectron. Reliab..

The ATPG Attack for Reverse Engineering of Combinational Hybrid Custom-Programmable Circuits

Houman Homayoun, Hamid Mahmoodi, Hassan Salmani, 2017 .

Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering

Houman Homayoun, Setareh Rafatirad, Hamid Mahmoodi, 2018, ACM Trans. Design Autom. Electr. Syst..

Deep RNN-Oriented Paradigm Shift through BOCANet: Broken Obfuscated Circuit Attack

Fatemeh Tehranipoor, Nima Karimian, Hamid Mahmoodi, 2018, ACM Great Lakes Symposium on VLSI.

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Kaushik Roy, Farshad Moradi, Hamid Mahmoodi, 2014, Microelectron. J..

A leakage control system for thermal stability during burn-in test

Kaushik Roy, Hamid Mahmoodi, Mesut Meterelliyoz, 2005, IEEE International Conference on Test, 2005..

Modeling read SNM considering both soft oxide breakdown and negative bias temperature instability

Behzad Ebrahimi, Ali Afzali-Kusha, Hamid Mahmoodi, 2012, Microelectron. Reliab..

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering

Kaushik Roy, Hunsoo Choo, Hamid Mahmoodi, 2010, J. Signal Process. Syst..

Modeling and testing of SRAM for new failure mechanisms due to process variations in nanoscale CMOS

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, IEEE Journal of Solid-State Circuits.

A process-tolerant cache architecture for improved yield in nanoscale technologies

Kaushik Roy, Amit Agarwal, Animesh Datta, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Process variation tolerant online current monitor for robust systems

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, 11th IEEE International On-Line Testing Symposium.

Data-dependant sense-amplifier flip-flop for low power applications

Kaushik Roy, Ashish Goel, Farshad Moradi, 2010, IEEE Custom Integrated Circuits Conference 2010.

Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits

Houman Homayoun, Hamid Mahmoodi, Hassan Salmani, 2016, 2016 29th IEEE International System-on-Chip Conference (SOCC).

Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005 .

Impact of technology scaling on performance of domino logic in nano-scale CMOS

Hamid Mahmoodi, Abhishek Guar, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

Resistive Computation: A Critique

Houman Homayoun, Manish Arora, Dean M. Tullsen, 2014, IEEE Computer Architecture Letters.

Data-retention flip-flops for power-down applications

Kaushik Roy, Hamid Mahmoodi, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors

Houman Homayoun, Tinoosh Mohsenin, Hamid Mahmoodi, 2014, GLSVLSI '14.

Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology

Hamid Mahmoodi, Vikram G. Rao, H. Mahmoodi, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Static Design of Spin Transfer Torques Magnetic Look Up Tables for ASIC Designs

Hamid Mahmoodi, Tyler David Sheaves, Aliyar Attaran, 2018, ACM Great Lakes Symposium on VLSI.

Power reduction in test-per-scan BIST with supply gating and efficient scan partitioning

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, Sixth international symposium on quality electronic design (isqed'05).

Efficient power clock generation for adiabatic logic

Ali Afzali-Kusha, Hamid Mahmoodi, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Impact of NBTI on performance of domino logic circuits in nano-scale CMOS

Reza Lotfi, Hamid Mahmoodi, Khalil Mafinezhad, 2011, Microelectron. J..

Domino logic designs for high-performance and leakage-tolerant applications

Elena I. Vatajelu, Farshad Moradi, Ali Peiravi, 2013, Integr..

Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style

Kaushik Roy, Hamid Mahmoodi, K. Roy, 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

PREDICTING WEEKLY DISCHARGE USING ARTIFICIAL NEURAL NETWORK (ANN) OPTIMIZED BY ARTIFICIAL BEE COLONY (ABC) A LGORITHM : A C ASE STUDY

Hamid Mahmoodi, Mahmood Rahsepar, H. Mahmoodi, 2014 .

Comparative BTI reliability analysis of SRAM cell designs in nano-scale CMOS technology

Hamid Mahmoodi, Shreyas Kumar Krishnappa, 2011, 2011 12th International Symposium on Quality Electronic Design.

Dual-edge triggered level converting flip-flops

Kaushik Roy, Hamid Mahmoodi, K. Roy, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Energy recovery clocking scheme and flip-flops for ultra low-energy applications

Kaushik Roy, Hamid Mahmoodi, Matthew Cooke, 2003, ISLPED '03.

An analytical model for read static noise margin including soft oxide breakdown, negative and positive bias temperature instabilities

Behzad Ebrahimi, Ali Afzali-Kusha, Hamid Mahmoodi, 2013, Microelectron. Reliab..

Dual-edge triggered static pulsed flip-flops

Hamid Mahmoodi, Aliakbar Ghadiri, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Hybrid STT-CMOS designs for reverse-engineering prevention

Houman Homayoun, Kris Gaj, Hamid Mahmoodi, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Low-overhead design technique for calibration of maximum frequency at multiple operating points

Swarup Bhunia, Hamid Mahmoodi, Somnath Paul, 2007, ICCAD 2007.

Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2005, Sixth international symposium on quality electronic design (isqed'05).

A high speed and leakage-tolerant domino logic for high fan-in gates

Farshad Moradi, Ali Peiravi, Hamid Mahmoodi, 2005, ACM Great Lakes Symposium on VLSI.

Power and energy reduction of racetrack-based caches by exploiting shared shift operations

Mehdi Kamal, Ali Afzali-Kusha, Hamid Mahmoodi, 2016, 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Reliability enhancement of power gating transistor under time dependent dielectric breakdown

Hamid Mahmoodi, 2012, 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

Kaushik Roy, Hamid Mahmoodi, Matthew Cooke, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dynamic single and Dual Rail spin transfer torque look up tables with enhanced robustness under CMOS and MTJ process variations

Houman Homayoun, Hamid Mahmoodi, Hassan Salmani, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

Double-gate SOI devices for low-power and high-performance applications

Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Low-Power and Variation-Tolerant Memory Design

Hamid Mahmoodi, H. Mahmoodi, 2011, Low-Power Variation-Tolerant Design in Nanometer Silicon.

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Ultra low power full adder topologies

Farshad Moradi, Ali Peiravi, Hamid Mahmoodi, 2009, 2009 IEEE International Symposium on Circuits and Systems.

On Custom LUT-based Obfuscation

Avesta Sasan, Houman Homayoun, Gaurav Kolhe, 2019, ACM Great Lakes Symposium on VLSI.

Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS

Hamid Mahmoodi, Roberto Menchaca, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Low-power scan design using first-level supply gating

Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Comparative analysis of robustness of spin transfer torque based look up tables under process variations

Houman Homayoun, Hamid Mahmoodi, Hassan Salmani, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Statistical design and optimization of SRAM cell for yield enhancement

Kaushik Roy, Hamid Mahmoodi, Saibal Mukhopadhyay, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices

Kaushik Roy, Ashish Goel, Animesh Datta, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Low-Power SRAM Using Bit-Line Charge-Recycling

Kaushik Roy, Hamid Mahmoodi, Keejong Kim, 2008, IEEE Journal of Solid-State Circuits.

Virtual Age: Enabling Technologies and Trends

Hamid Mahmoodi, Ali A. Jalali, 2009, 2009 Sixth International Conference on Information Technology: New Generations.

ANALYSIS OF IMPACT OF TRANSISTOR AGING EFFECTS ON CLOCK SKEW IN NANO-SCALE CMOS

Hao Jiang, Hamid Mahmoodi, Mandeep Singh Randhawa, 2012 .