Justin E. Harlow

A Novel Approach for Variation Aware Power Minimization during Gate Sizing

N. Ranganathan, Venkataraman Mahalingam, Justin E. Harlow, 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.

Design of experiments and evaluation of BDD ordering heuristics

Franc Brglez, Justin E. Harlow, 2001, International Journal on Software Tools for Technology Transfer.

Overview of Popular Benchmark Sets

Justin E. Harlow, J. Harlow, 2000, IEEE Des. Test Comput..

Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations

Franc Brglez, Justin E. Harlow, F. Brglez, 1998, FMCAD.

The open shop interactive mask design operation at harris semiconductor

Justin E. Harlow, 1977, DAC '77.

Architectures for silicon nanoelectronics and beyond

Massoud Pedram, Diana Marculescu, Alex Orailoglu, 2007, Computer.

ANovelApproach forVariation Aware PowerMinimization during GateSizing

V. Mahalingam, Nagarajan Ranganathan, Justin E. Harlow, 2006 .

Design of experiments in BDD variable ordering: lessons learned

Franc Brglez, Justin E. Harlow, 1998, ICCAD.

Toward design technology in 2020: trends, issues, and challenges [VLSI design]

Justin E. Harlow, 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

Guest Editors' Introduction: Benchmarking for Design and Test

Scott Davidson, Justin E. Harlow, 2000, IEEE Des. Test Comput..

Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking

Nevin Kapur, Franc Brglez, Debabrata Ghosh, 1998, Proceedings Design, Automation and Test in Europe.