P. Yang

Direct moat isolation for VLSI

K.L. Wang, S.A. Saller, W.R. Hunter, 1982, IEEE Transactions on Electron Devices.

Multilevel metal capacitance models for CAD design synthesis systems

P. Yang, P.-C. Li, J.-H. Chern, 1992, IEEE Electron Device Letters.

Direct evidence supporting the premises of a two-dimensional diode model for the parasitic thyristor in CMOS circuits built on thin epi

J.A. Seitchik, P. Yang, J.-H. Chern, 1988, IEEE Electron Device Letters.

An improved circuit model for CMOS latchup

J.A. Seitchik, P. Yang, L.A. Arledge, 1985, IEEE Electron Device Letters.

An Efficient SER Simulator for Dram Circuits-Including Transient and Substrate Structure Effects

P. Yang, J. A. Seitchik, K. C. Weng, 1986, 1986 Symposium on VLSI Technology. Digest of Technical Papers.