Muhammad H. Rais

发表

Braun's Multipliers: Spartan-3AN based Design and Implementation

Muhammad H. Rais, Mohammed H. Al Mijalli, 2011 .

Efficient FPGA Realization of S-Box using Reduced Residue of Prime Numbers

Saudi Arabia, Syed Manzoor Qasim, Muhammad H. Rais, 2010 .

FPGA implementation of Rijndael algorithm using reduced residue of prime numbers

Muhammad H. Rais, Syed M. Qasim, 2009, 2009 4th International Design and Test Workshop (IDT).

HARDWARE DESIGN AND IMPLEMENTATION OF FIXED‐WIDTH STANDARD AND TRUNCATED 4×4, 6×6, 8×8 and 12×12‐BIT MULTIPLIERS USING FPGA

Muhammad H. Rais, 2010 .

Virtex-5 Based Delay Study and Realization of Braun's Multipliers

Saudi Arabia, Muhammad H. Rais, Mohammed H. Al Mijalli, 2012 .

Field Programmable Gate Arrays Based Realization of Truncated Multipliers

Muhammad H. Rais, Mohammed H. Al Mijalli, 2011 .

FPGA design and implementation of fixed width standard and truncated 6×6-bit multipliers: A comparative study

Muhammad H. Rais, 2009, 2009 4th International Design and Test Workshop (IDT).

Efficient Hardware Realization of Advanced Encryption Standard Algorithm using Virtex-5 FPGA

Saudi Arabia, Syed Manzoor Qasim, Muhammad H. Rais, 2009 .

VIRTEX‐5 FPGA IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD ALGORITHM

Syed Manzoor Qasim, Muhammad H. Rais, 2010 .

Delay Study of Spartan-3A Field Programmable Gate Array

Saudi Arabia, Muhammad H. Rais, Mohammed H. Al Mijalli, 2012 .

Hardware Implementation of Truncated Multipliers Using Spartan-3AN, Virtex-4 and Virtex-5 FPGA Devices

Muhammad H. Rais, 2010 .

The Comparative Study of Spartan-3A and Virtex-5 Based Realization of S-Boxes

Saudi Arabia, Muhammad H. Rais, Mohammed H. Al Mijalli, 2013 .

Design and Field Programmable Gate Array Implementation of Basic Building Blocks for Power-Efficient Baugh-Wooley Multipliers

Muhammad H. Rais, Bandar M. Al-Harthi, Saad I. Al-Askar, 2010 .

Truncated Multipliers: A FPGA Realization

Saudi Arabia, Muhammad H. Rais, Mohammed H. Al Mijalli, 2013 .

Virtex-5 FPGA Based Braun's Multipliers

Saudi Arabia, Muhammad H. Rais, Mohammed H. Al Mijalli, 2011 .

A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box

Saudi Arabia, Syed Manzoor Qasim, Muhammad H. Rais, 2009 .

FPGA Based Fixed Width 4×4, 6×6, 8×8 and 12×12-Bit Multipliers using Spartan-3AN

Muhammad H. Rais, Mohamed H. Al Mijalli, 2011 .

Efficient Hardware Realization of Truncated Multipliers using FPGA

Muhammad H. Rais, 2009 .

Field Programmable Gate Arrays based Design, Implementation and Delay Study of Braun's Multipliers

Muhammad H. Rais, Mohammed H. Al Mijalli, 2011 .

Resource Efficient Design and Implementation of Standard and Truncated Multipliers using FPGAs

Muhammad H. Rais, Mohamed H. Al Mijalli, Mohammad Nisar, 2011 .

Resource Efficient Implementation of S-Box Based on Reduced Residue of Prime Numbers using Virtex-5 FPGA

Muhammad H. Rais, Syed M. Qasim, 2010 .