H. Terai

One point search and population based search Hardware Architecture for Hybrid Genetic Algorithm

Hironori Yamauchi, M. Yoshikawa, H. Terai, 2007 .

GA Processor Architecture for Real-Time GA Processing and VLSI Implementation for High-Speed PE

Hironori Yamauchi, M. Yoshikawa, Tetsuya Imai, 2004 .

A GA-based Floorplanning method for Topological Constraint

Hidekazu Terai, Masaya Yoshikawa, M. Yoshikawa, 2005 .

Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization

Hidekazu Terai, Masaya Yoshikawa, M. Yoshikawa, 2008, IEEE Games Entertainment Media Conference.

Research in Design Automation for VLSI Layout

Hidekazu Terai, Tokinori Kozawa, H. Terai, 1985, IEEE Design & Test of Computers.

Architecture for High Speed Learning of Neural Network using Genetic Algorithm

Hidekazu Terai, Masaya Yoshikawa, M. Yoshikawa, 2005 .

Performance‐driven placement procedure for low power

Hidekazu Terai, Masaya Yoshikawa, M. Yoshikawa, 2005 .

Crosstalk-driven placement based on genetic algorithms

H. Terai, M. Yoshikawa, M. Yoshikawa, 2004, 2004 IEEE International Conference onComputational Intelligence for Measurement Systems and Applications, 2004. CIMSA..