Suraj Kumar Saw

发表

A power efficient PFD-CP architecture for high speed clock and data recovery application

Alak Majumder, Vijay Nath, Madhusudan Maiti, 2019, Microsystem Technologies.

An ultra low power and low phase noise current starved CMOS VCO for wireless application

Vijay Nath, Suraj Kumar Saw, 2015, 2015 International Conference on Industrial Instrumentation and Control (ICIC).

Design and Implementation of TG Based D Flip Flop for Clock and Data Recovery Application

Preetisudha Meher, Suraj Kumar Saw, Swarnendu K Chakraborty, 2016 .

A 6nW CMOS operational amplifier for bio-medical and sensor applications

Vijay Nath, Abhishek Pandey, Subhra Chakraborty, 2015, 2015 Global Conference on Communication Technologies (GCCT).

Low-Cost Bluetooth-Arduino Hover Control Design of a Quad Copter

Puja Singh, Suraj Kumar Saw, Supantha Mandal, 2016 .

Low cost arduino wifi bluetooth integrated path following robotic vehicle with wireless GUI remote control

Suraj Kumar Saw, Sanjay Kumar, Supantha Mandal, 2016, 2016 International Conference on Information Communication and Embedded Systems (ICICES).

Analysis of a Self-compensating, Low-Noise, Low-Power PLL Circuit @ 45-nm Technology Node

Vijay Nath, Agnish Mal, Suraj Kumar Saw, 2017 .

A hybrid design approach of PVT tolerant, power efficient ring VCO

Alak Majumder, Abir J. Mondal, Madhusudan Maiti, 2020 .

Design and Analysis of Dual Modulus Prescaler Circuit for Frequency Synthesizer

Preetisudha Meher, Madhusudan Maiti, Suraj Kumar Saw, 2019, 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS).

A Dynamic Current Mode D-Flipflop for High Speed Application

Alak Majumder, Anupama Paul, Madhusudan Maiti, 2019, 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech).

A design approach of higher oscillation VCO made of CS amplifier with varying active load

Alak Majumder, Abir J. Mondal, Sandeep Kumar Yadav, 2020, Microsystem Technologies.

Performance Analysis of Low Power CSVCO for PLL Architecture

Vijay Nath, Suraj Kumar Saw, 2015, 2015 Second International Conference on Advances in Computing and Communication Engineering.

Passive element free variation aware decision circuit for 40 Gb/s CDR application

Alak Majumder, Madhusudan Maiti, Suraj Kumar Saw, 2020 .

Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication

Alak Majumder, Abir J. Mondal, Suraj Kumar Saw, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 1.37nW CMOS temperature sensor with sensing range of −25°C to 65°C

Vijay Nath, Abhishek Pandey, Subhra Chakraborty, 2015, 2015 Global Conference on Communication Technologies (GCCT).

An energy efficient PVT aware novel CML-TG based Mux-Latch circuit Serializes high rate data

Alak Majumder, Suraj Kumar Saw, Monalisa Das, 2018 .

A darlington pair transistor based operational amplifier

Vijay Nath, Abhishek Pandey, Subhra Chakraborty, 2015, 2015 Global Conference on Communication Technologies (GCCT).

An Ultra Low Power Fast Locking CMOS Phase Locked Loop for Wireless Communication

Vijay Nath, Suraj Kumar Saw, Bharat Gupta, 2015 .

A low power low noise current starved CMOS VCO for PLL

Vijay Nath, Suraj Kumar Saw, 2015, International Conference on Computing, Communication & Automation.