William B. Toms

发表

Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA

Doug A. Edwards, Jim D. Garside, Mahdi Jelodari Mamaghani, 2014, 2014 17th Euromicro Conference on Digital System Design.

Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling

Javier Navaridas, Mikel Luján, William B. Toms, 2016, IEEE Computer Architecture Letters.

Self-Timed Section-Carry Based Carry Lookahead Adders and the Concept of Alias Logic

P. Balasubramanian, William B. Toms, David A. Edwards, 2013, J. Circuits Syst. Comput..

Redundant Logic Insertion and Latency Reduction in Self-Timed Adders

P. Balasubramanian, William B. Toms, David A. Edwards, 2012, VLSI Design.

Delay-insensitive, point-to-point interconnect using m-of-n codes

William B. Toms, William John Bainbridge, David A. Edwards, 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

Indicating combinational logic decomposition

William B. Toms, David A. Edwards, 2011, IET Comput. Digit. Tech..

Architectural support for task scheduling: hardware scheduling for dataflow on NUMA systems

Salman Khan, Paolo Faraboschi, Mikel Luján, 2015, The Journal of Supercomputing.

Efficient synthesis of speed-independent combinational logic circuits

William B. Toms, David A. Edwards, 2005, ASP-DAC.

A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths

William B. Toms, David A. Edwards, D. A. Edwards, 2010, 2010 10th International Conference on Application of Concurrency to System Design.

The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation

Mikel Luján, William B. Toms, Oscar Palomar, 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Synthesising heterogeneously encoded systems

William B. Toms, David A. Edwards, Andrew Bardsley, 2006, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06).

M-of-N Code Decomposition for Indicating Combinational Logic

William B. Toms, David A. Edwards, D. A. Edwards, 2010, 2010 IEEE Symposium on Asynchronous Circuits and Systems.

Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks

Doug A. Edwards, William B. Toms, D. Edwards, 2009, 2009 15th IEEE Symposium on Asynchronous Circuits and Systems.

Energy Efficient Power-Management for Out-of-Order Processors Using Cyclic Power-Gating

Mikel Luján, William B. Toms, John Goodacre, 2021, ARCS.