Kenichi Osada

Chip-level TSV Process for Development of 3D System LSIs

Futoshi Furuta, Kazuyuki Hozawa, Kenichi Takeda, 2013 .

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators

Koichiro Ishibashi, Hiroyuki Mizuno, Tokuo Kure, 1996 .

Reliable Memory Cell Design for Environmental Radiation-Induced Failures in SRAM

Eishi Ibe, Kenichi Osada, E. Ibe, 2011 .

Reviews andProspects ofNanoscale SRAMs

Kenichi Osada, 2006 .

SP 24.4: A 2ns Access, 285MHz, Two-Port Cache Macro using Double Global Bit-Line Pairs

Kenichi Osada, Hisayuki Higuchi, Koichiro Ishibashi, 1997 .

ISLPED 2011 Symposium Organization

Naehyuck Chang, Yu Wang, Jian-Jia Chen, 2011 .

The Performance and Density Advantages of 3D FPGA

Tadayuki Matsumura, Kenichi Takeda, Naoto Miyamoto, 2012 .

Performance comparison of 2D and 3D FPGAs using true-3D CAD tool

Tadahiro Ohmi, Naoto Miyamoto, Tadayuki Matsumura, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).