Yuhwan Ro

Selective DRAM cache bypassing for improving bandwidth on DRAM/NVM hybrid main memory systems

Min Chul Sung, Jung Ho Ahn, Yuhwan Ro, 2017, IEICE Electron. Express.

Reducing memory access latency with asymmetric DRAM bank organizations

O Seongil, Jung Ho Ahn, Yuhwan Ro, 2013, ISCA.

Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices

Sukhan Lee, Jung Ho Ahn, Nam Sung Kim, 2018, IEEE Access.

SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures

Jung Ho Ahn, Yuhwan Ro, Jae W. Lee, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Understanding power-performance relationship of energy-efficient modern DRAM devices

Sukhan Lee, Jung Ho Ahn, Nam Sung Kim, 2017, 2017 IEEE International Symposium on Workload Characterization (IISWC).

SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture

Jung Ho Ahn, Yuhwan Ro, Jae W. Lee, 2017, IEEE Computer Architecture Letters.

Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond

Yuhwan Ro, Kyomin Sohn, Kwang-Il Park, 2021, 2021 IEEE Hot Chips 33 Symposium (HCS).

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

O Seongil, Nam Sung Kim, Yuhwan Ro, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).