Eduard Cerny

发表

Consistency, Causality and Compatibility

Eduard Cerny, B. Berkane, P. Girodias, 1998 .

Tautology checking using cross-controllability and cross-observability relations

Eduard Cerny, C. Mauras, E. Cerny, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

CBS-CAD: a CAD process management system

Michel Dagenais, Eduard Cerny, A. Kabbaj, 1993 .

Algorithm for the graph-partitioning problem using a problem transformation method

Eduard Cerny, El Mostapha Aboulhamid, Mohamed Meknassi, 1992, Comput. Aided Des..

Assertion System Functions and Tasks

Eduard Cerny, John Havlicek, Surrendra Dudani, 2010 .

Description and verification of RTL designs using multiway decision graphs

Francisco Corella, Eduard Cerny, Zijian Zhou, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

Compositional verification using interface recognizers/suppliers (irs)

Eduard Cerny, Mohammad-Sadegh Jahanpour, 2001 .

Verification Methodology Manual for SystemVerilog

Eduard Cerny, Alan Hunter, Janick Bergeron, 2005 .

Some Experience with the Use of Formal Specifications

Gregor von Bochmann, Eduard Cerny, Claude Jard, 1982, PSTV.

Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints

Eduard Cerny, Henrik Hulgaard, Fen Jin, 1998, FMCAD.

Simulation of MOS Circuits by Decision Diagrams

Eduard Cerny, Jan Gecsei, 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs (MDGs)

Xiaoyu Song, Eduard Cerny, Otmane Aït Mohamed, 2004, Comput. J..

A compositional transformation for formal verification

Eduard Cerny, 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Hierarchical Annotated Action Diagrams

Eduard Cerny, B. Berkane, P. Girodias, 1998 .

Multiway decision graphs and their applications in automatic formal verification of rtl designs

Xiaoyu Song, Eduard Cerny, Zijian Zhou, 1997 .

Improving Termination of MDG-Based Abstract State Enumeration via Term Schematization

Eduard Cerny, Sophie Renault, 1999, Electron. Notes Theor. Comput. Sci..

Propagation of last-transition-time constraints in gate-level timing analysis

Eduard Cerny, Maroun Kassab, Sidi Aourid, 1998, Proceedings Design, Automation and Test in Europe.

MDG Tools for the Verification of RTL Designs

Sofiène Tahar, Xiaoyu Song, Francisco Corella, 1996, CAV.

Hierarchical annotated action diagrams : an interface-oriented specification and verification method

Eduard Cerny, P. Girodias, Karim Khordoc, 1998 .

MDG-Based State Enumeration By Retiming And Circuit Transformation

Sofiène Tahar, Xiaoyu Song, Eduard Cerny, 2004, J. Circuits Syst. Comput..

CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools

Eduard Cerny, S. Fauvel, L.-P. Demers, 1987, 24th ACM/IEEE Design Automation Conference.

An object-oriented swicth-level simulator

Eduard Cerny, Jan Gecsei, L.-P. Demers, 1985, DAC.

Formal Verification and Models

Eduard Cerny, John Havlicek, Surrendra Dudani, 2010 .

An Approach to Unified Methodology of Combinational Switching Circuits

Eduard Cerny, Miguel A. Marin, 1977, IEEE Transactions on Computers.

Comparing Generic State Machines

Eduard Cerny, Michel Langevin, E. Cerny, 1991, CAV.

Michel Dagenais, Eduard Cerny, Anas Kabbaj, 1991, Proceedings of the European Conference on Design Automation..

Integrating mdg variable ordering in a vhdl-mdg design verification system

Yi Feng, Eduard Cerny, 2002 .

A recursive technique for computing lower-bound performance of schedules

Eduard Cerny, Michel Langevin, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Some issues in protocol implementation testing

Eduard Cerny, 1984, Computer Communication Review.

A Class of Test Generators for Built-In Testing

Eduard Cerny, El Mostapha Aboulhamid, 1983, IEEE Transactions on Computers.

Verification of I/O trace set inclusion for a class of non-deterministic finite state machines

Eduard Cerny, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Modeling cell processing hardware with action diagrams

Eduard Cerny, Karim Khordoc, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Modeling and Automatic Formal Verification of the Fairisle ATM Switch Fabric using MDGs

Sofiène Tahar, Eduard Cerny, Xiaoyu Song, 1997 .

Verification with Abstract State Machines Using MDGs

Sofiène Tahar, Xiaoyu Song, Francisco Corella, 1997, Formal Hardware Verification.

Formal verification of an ATM switch fabric using multiway decision graphs

Sofiène Tahar, Xiaoyu Song, Eduard Cerny, 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.

Model Reductions and a Case Study

Eduard Cerny, Jin Hou, E. Cerny, 2000, FMCAD.

Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems : proceedings of the IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications, 20-25 April 1997, Toledo, Spain

Carlos Delgado Kloos, Eduard Cerny, 1997 .

Comments on "Equational Logic"

Eduard Cerny, 1976, IEEE Trans. Computers.

An extended OBDD representation for extended FSMs

Eduard Cerny, Michel Langevin, 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

Practical Application of Formal Verification Techniques on a Frame Mux/Demux Chip from Nortel Semiconductors

Ying Liu, Eduard Cerny, Ying Xu, 1999, CHARME.

Interface timing verification with delay correlation using constraint logic programming

Eduard Cerny, Pierre Girodias, E. Cerny, 1997, Proceedings European Design and Test Conference. ED & TC 97.

Controllability and Fault Observability in Modular Combinational Circuits

Eduard Cerny, 1978, IEEE Transactions on Computers.

Controllability and FaultObservabilityin Modular CombinationalCircuits

Eduard Cerny, 1978 .

Example: Interfacing ARM7 and a Static RAM

Eduard Cerny, B. Berkane, P. Girodias, 1998 .

Model partitioning and the performance of distributed timewarp simulation of logic circuits

Eduard Cerny, Jocelyn Cloutier, F. Guertin, 1997, Simul. Pract. Theory.

Multiway Decision Graphs for Automated Hardware Verification

Xiaoyu Song, Francisco Corella, Eduard Cerny, 1997, Formal Methods Syst. Des..

Automatic jog insertion for 2D mask compaction: a global optimization perspective

Eduard Cerny, G. Bois, J.-L. Martineau, 1992, [1992] Proceedings The European Conference on Design Automation.

A recursive technique for computing delays in series-parallel MOS transistor circuits

Nicholas C. Rumin, Eduard Cerny, Jean Paul Caisso, 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Self-Adjusting Networks for VLSI Simulation

Eduard Cerny, Jan Gecsei, 1987, IEEE Transactions on Computers.

HAAD VHDL Model

Eduard Cerny, B. Berkane, P. Girodias, 1998 .

Formal Characterization of HAAD

Eduard Cerny, B. Berkane, P. Girodias, 1998 .

Built-In Testing of One-Dimensional Unilateral Iterative Arrays

Eduard Cerny, El Mostapha Aboulhamid, 1984, IEEE Transactions on Computers.

MDG-based verification by retiming and combinational transformations

Xiaoyu Song, Eduard Cerny, Otmane Aït Mohamed, 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

Solving Linear, Min and Max Constraint Systems Using CLP Based on Relational Interval Arithmetic

Eduard Cerny, William J. Older, Pierre Girodias, 1997, Theor. Comput. Sci..

Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits

Bozena Kaminska, Eduard Cerny, Abdessatar Abderrahman, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An Apology for Local Variables

Eduard Cerny, John Havlicek, Surrendra Dudani, 2015 .

Model Checking for a First-Order Temporal Logic Using Multiway Decision Graphs

Xiaoyu Song, Francisco Corella, Eduard Cerny, 1998, CAV.

Use of Formal Specifications for Protocol Design, Implementation and Testing

Gregor von Bochmann, Eduard Cerny, Rachida Dssouli, 1984, PSTV.

Integrating Behavior and Timing in Executable Specifications

Eduard Cerny, Allan Silburt, Karim Khordoc, 1993, CHDL.

Fault Tolerance in a Class of Sorting Networks

Jianli Sun, Eduard Cerny, Jan Gecsei, 1994, IEEE Trans. Computers.

Introduction to Assertion Based Formal Verification

Eduard Cerny, John Havlicek, Surrendra Dudani, 2010 .

A class of fault-tolerant cellular permutation networks

Eduard Cerny, El Mostapha Aboulhamid, M. Eleuldj, 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

Mechanics of Local Variables

Eduard Cerny, John Havlicek, Surrendra Dudani, 2015 .

Synthesis of checker EFSMs from timing diagram specifications

Eduard Cerny, E. K. Ogoubi, E. Cerny, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

SystemVerilog Simulation Semantics

Eduard Cerny, John Havlicek, Surrendra Dudani, 2015 .

Verification of real time controllers against timing diagram specifications using constraint logic programming

Eduard Cerny, Fen Jin, 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).

Gate-level timing verification using waveform narrowing

Eduard Cerny, Jindrich Zejda, 1994, EURO-DAC '94.

A recursive technique for computing lower-bound performance of schedules

Eduard Cerny, Michel Langevin, 1996, TODE.

Term ordering problem on MDG

Yi Feng, Eduard Cerny, 2002, GLSVLSI '02.

Partitioning transition relations efficiently and automatically

Xiaoyu Song, Francisco Corella, Eduard Cerny, 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

Summary and Recent Developments

Eduard Cerny, B. Berkane, P. Girodias, 1998 .

Procedural Concurrent Assertions

Eduard Cerny, John Havlicek, Surrendra Dudani, 2010 .

Interface Verification using CLP

Eduard Cerny, B. Berkane, P. Girodias, 1998 .

Use of Fault Dropping for Multiple Fault Analysis

Eduard Cerny, El Mostapha Aboulhamid, Alain Verreault, 1994, IEEE Trans. Computers.

Experience with Formal Specifications Using an Extended State Transition Model

Gregor von Bochmann, Eduard Cerny, Claude Jard, 1982, IEEE Trans. Commun..

Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs

Sofiène Tahar, Xiaoyu Song, Francisco Corella, 1996, FMCAD.

SystemVerilog Language Overview

Eduard Cerny, John Havlicek, Surrendra Dudani, 2015 .

Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems

Carlos Delgado Kloos, Eduard Cerny, E. Cerny, 1997 .

Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS)

Eduard Cerny, M. S. Jahanpour, 2000, Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786).

On the non-termination of M-based abstract state enumeration

Xiaoyu Song, Eduard Cerny, Otmane Aït Mohamed, 1997, Theor. Comput. Sci..

Test pattern generation for multiple stuck-at faults

Eduard Cerny, El Mostapha Aboulhamid, Y. Karkouri, 1993, Proceedings ETC 93 Third European Test Conference.

Behavioral verification of an ATM switch fabric using implicit abstract state enumeration

Sofiène Tahar, Xiaoyu Song, Eduard Cerny, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

State enumeration with abstract descriptions of state machines

Xiaoyu Song, Francisco Corella, Eduard Cerny, 1995, CHARME.

Optimization-based multifrequency test generation for analog circuits

Bozena Kaminska, Eduard Cerny, Abdessatar Abderrahman, 1996, J. Electron. Test..

On the generation of test patterns for multiple faults

Eduard Cerny, El Mostapha Aboulhamid, Younès Karkouri, 1993, J. Electron. Test..

Bounding switching activity in CMOS circuits using constraint resolution

Nicholas C. Rumin, Eduard Cerny, Jindrich Zejda, 1996, Proceedings ED&TC European Design and Test Conference.

Local microcode generation in system design

Heinrich Theodor Vierhaus, Eduard Cerny, Jörg Wilberg, 1994, Code Generation for Embedded Processors.

Overview of HAAD Method

Eduard Cerny, B. Berkane, P. Girodias, 1998 .

Verification of real time controllers against timing diagram specifications using constraint logic programming

Eduard Cerny, Fen Jin, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Model partitioning and the performance of distributed timewarp simulation of logic circuits

Eduard Cerny, Jocelyn Cloutier, F. Guertin, 1997 .

Hardware Description Languages and their Applications

Carlos Delgado Kloos, Eduard Cerny, 1997, IFIP — The International Federation for Information Processing.

Semantics and verification of action diagrams with linear timing

Eduard Cerny, Karim Khordoc, 1998, TODE.

Supporting sequential assumptions in hybrid verification

Eduard Cerny, Kevin Harer, Pei-Hsin Ho, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Efficient generation of diagonal constraints for 2-D mask compaction

Eduard Cerny, Guy Bois, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An Algebraic Model for Asynchronous Circuits Verification

Eduard Cerny, Christian Berthet, 1988, IEEE Trans. Computers.

A Test Design Methodology for Protocol Testing

Gregor von Bochmann, Eduard Cerny, Behçet Sarikaya, 1987, IEEE Transactions on Software Engineering.

Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs

Sofiène Tahar, Xiaoyu Song, Eduard Cerny, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Functional Description of Connector-Switch-Attenuator Networks

Eduard Cerny, Jan Gecsei, 1988, IEEE Trans. Computers.

Fault-tolerance in balanced sorting networks

Jianli Sun, Eduard Cerny, Jan Gecsei, 1990, J. Electron. Test..

Let, Sequence and Property Declarations; Inference

Eduard Cerny, John Havlicek, Surrendra Dudani, 2015 .

Variable ordering on multiway decision graphs

Yi Feng, Eduard Cerny, E. Cerny, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

The Power of Assertions in SystemVerilog

Eduard Cerny, John Havlicek, Surrendra Dudani, 2010 .

Checkers in Formal Verification

Eduard Cerny, John Havlicek, Surrendra Dudani, 2015 .

Using Formalized Timing Diagrams in VHDL Simulation

Eduard Cerny, M. Dufresne, Karim Khordoc, 1992 .

SystemVerilog Language and Simulation Semantics Overview

Eduard Cerny, John Havlicek, Surrendra Dudani, 2010 .

A stimulus/response system based on hierarchical timing diagrams

Eduard Cerny, Karim Khordoc, Mario Dufresne, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Synthesis of Minimal Binary Decision Trees

Eduardo Sanchez, Eduard Cerny, Daniel Mange, 1979, IEEE Transactions on Computers.

Automated verification with abstract state machines using multiway decision graphs

Sofiène Tahar, Xiaoyu Song, Francisco Corella, 1997 .