Kozo Kinoshita

发表

Test Generation for Scan Design Circuits with Tri-State Modules and Bidirectional Terminals

Kozo Kinoshita, Hideo Fujiwara, Takuji Ogihara, 1983, 20th Design Automation Conference Proceedings.

On Processing Order for Obtaining Implication Relations in Static Learning

Kozo Kinoshita, Seiji Kajihara, Hideyuki Ichihara, 2000 .

On an effective selection of IDDQ measurement vectors for sequential circuits

Kozo Kinoshita, Seiji Kajihara, Hideyuki Ichihara, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

On test generation with a limited number of tests

Kozo Kinoshita, Seiji Kajihara, Hideyuki Ichihara, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement

Kozo Kinoshita, Hiroyuki Yotsuyanagi, Seiji Kajihara, 1995, IEICE Trans. Inf. Syst..

CIRCUIT DESIGN FOR BUILT-IN CURRENT TESTING

Kozo Kinoshita, Yukiya Miura, K. Kinoshita, 1992, Proceedings International Test Conference 1992.

Design for diagnosability of CMOS circuits

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

An approach to the analysis and detection of crosstalk faults in digital VLSI circuits

Xiaole Xu, Kozo Kinoshita, Noriyoshi Itazaki, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Automatic fault location using E-beam and LSI testers

Kozo Kinoshita, N. Itazaki, T. Sumioka, 1993, Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS).

A method for identifying robust dependent and functionally unsensitizable paths

Irith Pomeranz, Sudhakar M. Reddy, Kozo Kinoshita, 1997, Proceedings Tenth International Conference on VLSI Design.

Precise test generation for resistive bridging faults of CMOS combinational circuits

Kozo Kinoshita, Toshiyuki Maeda, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

A partial scan algorithm based on reduced scan shift

Kozo Kinoshita, Yoshinobu Higami, S. Kajihara, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits

Irith Pomeranz, Sudhakar M. Reddy, Kozo Kinoshita, 1993, 30th ACM/IEEE Design Automation Conference.

On low-capture-power test generation for scan testing

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Removal of redundancy in logic circuits under classification of undetectable faults

Kozo Kinoshita, Seiji Kajihara, Haruko Shiba, 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.

On compacting test sets by addition and removal of test vectors

Irith Pomeranz, Sudhakar M. Reddy, Kozo Kinoshita, 1994, Proceedings of IEEE VLSI Test Symposium.

SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Fault models and test generation for IDDQ testing: embedded tutorial

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, ASP-DAC.

Undetectable fault removal of sequential circuits based on unreachable states

Kozo Kinoshita, Hiroyuki Yotsuyanagi, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

IDDQ test vector selection for transistor short fault testing

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 1997, Systems and Computers in Japan.

An approach to the analysis and test of crosstalk faults in digital VLSI circuits

Xiaole Xu, Kozo Kinoshita, Noriyoshi Itazaki, 1991, Proceedings of the European Conference on Design Automation..

Cascade Realization of 3-Input 3-Output Conservative Logic Circuits

Kozo Kinoshita, Tsutomu Sasao, 1978, IEEE Transactions on Computers.

A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead

Kozo Kinoshita, Hideo Fujiwara, Kewal K. Saluja, 1985, ITC.

Crosstalk fault testing by the built‐in self‐test method with test points and phase shifters

Kozo Kinoshita, Kazuya Shimizu, Noriyoshi Itazaki, 2004 .

Synthesis of Sequential Circuits by Redundancy Removal and Retiming

Kozo Kinoshita, Hiroyuki Yotsuyanagi, Seiji Kajihara, 1997, J. Electron. Test..

Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits

Kozo Kinoshita, Yukiya Miura, Arabi Keshk, 2000, Proceedings of the Ninth Asian Test Symposium.

Built-In Self-Testing RAM: A Practical Alternative

Kozo Kinoshita, Kewal Saluja, Siew Sng, 1987, IEEE Design & Test of Computers.

Compaction of Test Sequences for IDDQ Testing

Kozo Kinoshita, Toshiyuki Maeda, 1999 .

Removal of redundancy in combinational circuits under classification of undetectable faults

Kozo Kinoshita, Seiji Kajihara, Haruko Shiba, 1993, Systems and Computers in Japan.

A diagnosis method for single logic design errors in gate-level combinational circuits

Kozo Kinoshita, Masahiro Numa, Seiji Kajihara, 1997 .

A diagnosis method for single logic design errors in gate-level combinational circuits

Kozo Kinoshita, Masahiro Numa, Seiji Kajihara, 1997, Systems and Computers in Japan.

Design of testing circuit and test generation for built-in current testing

Kozo Kinoshita, Yukiya Miura, Yasushi Wada, 1993, Systems and Computers in Japan.

Combinationally irredundant ISCAS-89 benchmark circuits

Kozo Kinoshita, I. Pomeranz, Sudhakar M. Reddy, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

Synthesis for testability by sequential redundancy removal using retiming

Kozo Kinoshita, Hiroyuki Yotsuyanagi, Seiji Kajihara, 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers.

Static test compaction for IDDQ testing of sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yoshinobu Higami, 1998, Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232).

Some Existence Theorems for Probabilistically Diagnosable Systems

Kozo Kinoshita, Hideo Fujiwara, 1978, IEEE Transactions on Computers.

On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 2005, IEICE Trans. Inf. Syst..

Estimation of possible errors in DNA computing

Kozo Kinoshita, Hiroshi Iwasaki, Tatsuo Yoshinobu, 1998 .

Fault diagnosis for physical defects of unknown behaviors

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 2003, 2003 Test Symposium.

Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis

Kozo Kinoshita, Seiji Kajihara, Rikiya Nishigaya, 1995, IEICE Trans. Inf. Syst..

I/sub DDQ/ current dependency on test vectors and bridging resistance

Arabi Keshk, Kozo Kinoshita, Yukiya Miura, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

An Integrated Computer Aided Design System for Gate Array Masterslices: Part 1. Logic Reorganization System Lores-2

Kozo Kinoshita, Takuji Ogihara, Shinichi Murai, 1981, 18th Design Automation Conference.

Partial scan design and test sequence generation based on reduced scan shift method

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1995, J. Electron. Test..

Design of High-Level Test Language for Digital LSI

Kozo Kinoshita, Takuji Okamoto, Hiroyuki Shibata, 1983, ITC.

Low power design and its testability

Kozo Kinoshita, Hiroaki Ueda, 1995, Proceedings of the Fourth Asian Test Symposium.

Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm

Kozo Kinoshita, Noriyoshi Itazaki, 1986, ITC.

Reducing scan shifts using folding scan trees

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2003, 2003 Test Symposium.

Design of a BIST RAM with row/column pattern sensitive fault detection capability

Kozo Kinoshita, Kewal K. Saluja, Manoj Franklin, 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

A New Method for Low-Capture-Power Test Generation for Scan Testing

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2006, IEICE Trans. Inf. Syst..

Compaction of IDDQ Test Sequence Using Reassignment Method

Kozo Kinoshita, Toshiyuki Maeda, K. Kinoshita, 1999, European Test Workshop 1999 (Cat. No.PR00390).

Fault Diagnosis of Physical Defects Using Unknown Behavior Model

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 2005, Journal of Computer Science and Technology.

Traffic Analysis of the Stop-and-Wait ARQ over a Markov Error Channel

Kozo Kinoshita, Masaharu Komatsu, Chun-Xiang Chen, 1994 .

Static test compaction for IDDQ testing of bridging faults in sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000 .

Test transformation to improve compaction by statistical encoding

Irith Pomeranz, Sudhakar M. Reddy, Kozo Kinoshita, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

On the evaluation of process-fault tolerance ability of CMOS integrated circuits

Kozo Kinoshita, Etienne Sicard, 1990, Proceedings. International Test Conference 1990.

Procedure to overcome the Byzantine General's problem for bridging faults in CMOS circuits

Arabi Keshk, Kozo Kinoshita, Yukiya Miura, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

A statistical error model for image sensors and its testing

Kozo Kinoshita, Hideyuki Ichihara, Hiroshi Uemura, 2007 .

Test pattern generation for crosstalk faults considering the gate delay

Kozo Kinoshita, Noriyoshi Itazaki, Hisao Naitoh, 1995, Systems and Computers in Japan.

A Redundancy Removal Method for Sequential Circuits Based on Unreachable States

Kozo Kinoshita, Hiroyuki Yotsuyanagi, Seiji Kajihara, 1998 .

Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults

Kozo Kinoshita, Toshiyuki Maeda, K. Kinoshita, 2000, Proceedings of the Ninth Asian Test Symposium.

Testable Designs of Sequential Circuits under Highly Observable Condition

Kozo Kinoshita, Xiaoqing Wen, K. Kinoshita, 1992, Proceedings International Test Conference 1992.

A Unified Procedure to Overcome the Byzantine General's Problem for Inter-gate and Intra-gate Bridging Faults in CMOS Circuits

Arabi Keshk, Kozo Kinoshita, Yukiya Miura, 2000 .

A high-speed IDDQ sensor implementation

Kozo Kinoshita, Shigeki Nishikawa, Yann Antonioli, 2000, Proceedings of the Ninth Asian Test Symposium.

Throughput performance of ARQ schemes on a markov bit‐error channel

Kozo Kinoshita, Masaharu Komatsu, Katsuaki Okamoto, 1995 .

Connection Assignments for Probabilistically Diagnosable Systems

Kozo Kinoshita, Hideo Fujiwara, 1978, IEEE Transactions on Computers.

Test generation for multiple faults based on parallel vector pair analysis

Kozo Kinoshita, S. Kajihara, Tetsuji Sumioka, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Fault detection and diagnosis of k-UCP circuits under totally observable condition

Kozo Kinoshita, Xiaoqing Wen, K. Kinoshita, 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

Compaction of IDDQ test sequence using reassignment method

Kozo Kinoshita, Toshiyuki Maeda, 1999, ETW.

Efficient Methods for Guided-Probe Diagnosis (Special Issue on VLSI Testing and Testable Design)

Kozo Kinoshita, Noriyoshi Itazaki, Wen Xiaoqing, 1993 .

Test sequence compaction by reduced scan shift and retiming

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1995, Proceedings of the Fourth Asian Test Symposium.

Evaluation of the maximum number of switching gates for CMOS circuits

Kozo Kinoshita, Hiroaki Ueda, 1995, Systems and Computers in Japan.

Built-in self-test for multiple CLB faults of a LUT type FPGA

Kozo Kinoshita, Noriyoshi Itazaki, Yasuyuki Matsumoto, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

A new ATPG method for efficient capture power reduction during scan testing

Kozo Kinoshita, Kohei Miyase, Kewal K. Saluja, 2006, 24th IEEE VLSI Test Symposium.

LORES - Logic Reorganization System

Kozo Kinoshita, Hideo Fujiwara, Shinichi Murai, 1978, 15th Design Automation Conference.

Logic Optimization: Redundancy Addition and Removal Using Implication Relations

Kozo Kinoshita, Hideyuki Ichihara, 1998 .

Built-in Self-Test for crosstalk faults in a digital VLSI

Kozo Kinoshita, Kazuya Shimizu, Noriyoshi Itazaki, 2002, Systems and Computers in Japan.

Solution of the Knapsack Problem by Deoxyribonucleic Acid Computing

Kozo Kinoshita, Hiroshi Iwasaki, Tatsuo Yoshinobu, 1998 .

Observation time reduction for IDDQ testing of bridging faults in sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yoshinobu Higami, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits

Irith Pomeranz, Sudhakar M. Reddy, Kozo Kinoshita, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Throughput Analysis of ARQ Schemes in Dialogue Communication over Half-Duplex Line

Kozo Kinoshita, Masaharu Komatsu, Chun-Xiang Chen, 1994 .

Test Sequence Generation for Sequential Circuits with Distinguishing Sequences (Special Section on VLSI Design and CAD Algorithms)

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1993 .

A Per-Test Fault Diagnosis Method Based on the X-Fault Model

Kozo Kinoshita, Xiaoqing Wen, Kohei Miyase, 2006, IEICE Trans. Inf. Syst..

Fault simulation method for crosstalk faults in clock-delayed domino CMOS circuits

Kozo Kinoshita, Kazuya Shimizu, Noriyoshi Itazaki, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

Power Estimation and Reduction of CMOS Circuits Considering Gate Delay

Kozo Kinoshita, Hiroaki Ueda, 1999 .

A case study of mixed-signal integrated circuit testing: an application of current testing using the upper limit and the lower limit

Kozo Kinoshita, Yukiya Miura, Sachio Naito, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

On Invariant Implication Relations in Redundancy Removal for Combinational Circuits

Kozo Kinoshita, Hideyuki Ichihara, S. Kajihara, 1995 .

Static test compaction for IDDQ testing of bridging faults in sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, Systems and Computers in Japan.

Conservative Logic Elements and Their Universality

Kozo Kinoshita, Tsutomu Sasao, K. Kinoshita, 1979, IEEE Transactions on Computers.

A statistical error model for image sensors and its testing

Kozo Kinoshita, Hideyuki Ichihara, Hiroshi Uemura, 2007, Systems and Computers in Japan.

A Design of Programmable Logic Arrays with Universal Tests

Kozo Kinoshita, Hideo Fujiwara, 1981, IEEE Transactions on Computers.

A BIST Circuit for IDDQ Tests

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2003 .

On invariant implication relations for removing partial circuits

Kozo Kinoshita, Seiji Kajihara, Hideyuki Ichihara, 1997, Systems and Computers in Japan.

On Magnetic Bubble Logic Circuits

Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda, 1976, IEEE Transactions on Computers.

Efficient techniques for reducing IDDQ observation time for sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yoshinobu Higami, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

A new testable design of logic circuits under highly observable condition

Kozo Kinoshita, Hideo Tamamoto, Wen Xiaoqing, 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

On per-test fault diagnosis using the X-fault model

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2004, ICCAD 2004.

Stuck-open faults test generation for cmos combinational circuits

Kozo Kinoshita, Noriyoshi Itazaki, Seiji Kajihara, 1991, Systems and Computers in Japan.

Easily Testable Sequential Machines with Extra Inputs

Kozo Kinoshita, Tsutomu Sasao, Hideo Fujiwara, 1975, IEEE Transactions on Computers.

Test pattern generation for circuits with tri-state modules by Z-algorithm

Kozo Kinoshita, Noriyoshi Itazaki, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Fault diagnosis for static CMOS circuits

Kozo Kinoshita, Hideo Tamamoto, Kewal K. Saluja, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

An algorithmic test generation method for crosstalk faults in synchronous sequential circuits

Kozo Kinoshita, Noriyoshi Itazaki, Yasutaka Idomoto, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Computer Reliability and Fault Tolerant Technology

Kozo Kinoshita, 1984 .

Testing of k-FR Circuits under Highly Observable Condition

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 1995, IEICE Trans. Inf. Syst..

Throughput Performances of ARQ Protocols Operating over Generalized Two-State Markov Error Channel

Kozo Kinoshita, Masaharu Komatsu, Yukuo Hayashida, 1994 .

On per-test fault diagnosis using the X-fault model

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Low-capture-power test generation for scan-based at-speed testing

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2005, IEEE International Conference on Test, 2005..

Transistor Leakage Fault Diagnosis for CMOS Circuits

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 1998 .

I/sub DDQ/ sensing technique for high speed IDDQ testing

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2001, Proceedings 10th Asian Test Symposium.

Reduced scan shift: a new testing method for sequential circuits

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1994, Proceedings., International Test Conference.

CIRCEL;VLSI/CAD software tools for IC layout design with logic cell compiler on - line analog simulator and process fault simulator.

Kozo Kinoshita, Etienne Sicard, 1989 .

On the Effect of Size of Fault Word in Parallel Fault Simulation

Kozo Kinoshita, Yuzo Takamatsu, 1987 .

Fault simulation techniques to reduce IDDQ measurement vectors for sequential circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 1999, Proceedings Eighth Asian Test Symposium (ATS'99).

Transistor leakage fault location with I/sub DDQ/ measurement

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 1995, Proceedings of the Fourth Asian Test Symposium.

On configuring scan trees to reduce scan shifts based on a circuit structure

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.

Test sequence compaction for sequential circuits with reset states

Kozo Kinoshita, Yuzo Takamatsu, Yoshinobu Higami, 2000, Proceedings of the Ninth Asian Test Symposium.

Testing Core-Based System-on-a-Chip Designs

Kozo Kinoshita, Xiaoqing Wen, Kewal K. Saluja, 2001 .

A high speed I/sub DDQ/ sensor for low-voltage ICs

Kozo Kinoshita, Masaki Hashizume, Takeomi Tamesada, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

IDDQ test vector selection for transistor short fault testing

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 1997 .

Current-based testable design of level shifters in liquid crystal display drivers

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2010, 2010 15th IEEE European Test Symposium.

A testable design of logic circuits under highly observable condition

Kozo Kinoshita, Xiaoqing Wen, K. Kinoshita, 1990, Proceedings. International Test Conference 1990.

Sequential Machines Capable of Fault Diagnosis

Kozo Kinoshita, Hiroshi Ozaki, Shin-ichi Murakami, 1970, IEEE Transactions on Computers.

Traffic analysis of a hybrid go‐back‐n arq scheme using repeated transmissions

Kozo Kinoshita, Masaharu Komatsu, Yukuo Hayashida, 1994 .

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

Kozo Kinoshita, Xiaoqing Wen, Kohei Miyase, 2008, J. Electron. Test..

Cascade realization 3-input 3-output conservative logic circuits — application of three-valued logic to two-valued logic —

Kozo Kinoshita, Tsutomu Sasao, 1976 .

Transistor Leakage Fault Diagnosis with I DDQ and Logic Information

Kozo Kinoshita, Hideo Tamamoto, Kewal K. Saluja, 1998 .

Ligation errors in DNA computing.

Kozo Kinoshita, Hiroshi Iwasaki, Tatsuo Yoshinobu, 1999, Bio Systems.

Synthesis of Testable Sequential Circuits with Reduced Checking Sequences (Special Issue on VLSI Testing and Testable Design)

Kozo Kinoshita, Satoshi Shibatani, 1993 .

Design of Programmable Logic Arrays for Parallel Testing

Kozo Kinoshita, Kewal K. Saluja, C. Boswell, 1985, Comput. Syst. Sci. Eng..

Realization of Minimum Circuits with Two-Input Conservative Logic Elements

Kozo Kinoshita, Tsutomu Sasao, 1978, IEEE Transactions on Computers.

IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2002 .

A Testable Design of Logic Circuits under Highly Observable Condition

Kozo Kinoshita, Xiaoqing Wen, 1992, IEEE Trans. Computers.

Channel-Grouping Methods on Go-Back-N ARQ Scheme in Multiple-Parallel-Channel System

Kozo Kinoshita, Masaharu Komatsu, Chun-Xiang Chen, 1994 .

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits

Kozo Kinoshita, Kewal K. Saluja, Yuzo Takamatsu, 2000, J. Electron. Test..

Row/column pattern sensitive fault detection in RAMs via built-in self-test

Kozo Kinoshita, Kewal K. Saluja, Manoj Franklin, 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

A Novel ATPG Method for Capture Power Reduction during Scan Testing

Kozo Kinoshita, Xiaoqing Wen, Kohei Miyase, 2007, IEICE Trans. Inf. Syst..

Synthesis of easily testable sequential circuits with checking sequences

Kozo Kinoshita, S. Shibatani, 1992, Proceedings First Asian Test Symposium (ATS `92).

Consecutive Customer Loss Phenomenon due to Buffer Overflow in Finite Buffer Queueing System

Kozo Kinoshita, Masaharu Komatsu, 1993 .

Partially parallel scan chain for test length reduction by using retiming technique

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

Design of Diagnosable Sequential Machines Utilizing Extra Outputs

Kozo Kinoshita, Hideo Fujiwara, K. Kinoshita, 1974, IEEE Transactions on Computers.

Test generation for multiple faults based on parallel vector pair analysis

Kozo Kinoshita, Seiji Kajihara, Tetsuji Sumioka, 1993, ICCAD.

An Easily Testable Design of Programmable Logic Arrays for Multiple Faults

Kozo Kinoshita, Hideo Fujiwara, Kewal K. Saluja, 1983, IEEE Transactions on Computers.

On acceleration of logic circuits optimization using implication relations

Kozo Kinoshita, Hideyuki Ichihara, 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

Resynthesis for sequential circuits designed with a specified initial state

Kozo Kinoshita, Hiroyuki Yotsuyanagi, Seiji Kajihara, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Generation of test sequences for current testing

Kozo Kinoshita, Y. Wada, Y. Miura, 1991, [1991] Proceedings Pacific Rim International Symposium on Fault Tolerant Systems.

A BIST circuit for I/sub DDQ/ tests

Kozo Kinoshita, Masaki Hashizume, Hiroyuki Yotsuyanagi, 2003, 2003 Test Symposium.

CONT: a concurrent test generation system

Kozo Kinoshita, Yuzo Takamatsu, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Extended selection of switching target faults in CONT algorithm for test generation

Kozo Kinoshita, Yuzo Takamatsu, 1990 .

Channel width test data compression under a limited number of test inputs and outputs

Kozo Kinoshita, Hideyuki Ichihara, Shigeki Nishikawa, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Performance analysis of Go‐Back‐N ARQ scheme on parallel channel system

Kozo Kinoshita, Masaharu Komatsu, Chun-Xiang Chen, 1998 .

Extended selection of switching target faults in CONT algorithm for test generation

Kozo Kinoshita, Yuzo Takamatsu, 1990, J. Electron. Test..

Test Pattern Generation for API Faults in RAM

Kozo Kinoshita, Kewal K. Saluja, 1985, IEEE Transactions on Computers.

Efficient Guided-Probe Fault Location Method for Sequential Circuits

Kozo Kinoshita, Xiaoqing Wen, Hideo Tamamoto, 1995, IEICE Trans. Inf. Syst..

On the Number of Fanout-Free Functions and Unate Cascade Functions

Kozo Kinoshita, Tsutomu Sasao, 1979, IEEE Transactions on Computers.

A High-Speed IDDQ Sensor for Low-Voltage ICs

Kozo Kinoshita, Masaki Hashizume, Takeomi Tamesada, 1998 .

Foreword

Kozo Kinoshita, 2002, J. Electron. Test..

A fault simulation method for crosstalk faults in synchronous sequential circuits

Kozo Kinoshita, Noriyoshi Itazaki, Yasutaka Idomoto, 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

On the Computational Complexity of System Diagnosis

Kozo Kinoshita, Hideo Fujiwara, K. Kinoshita, 1978, IEEE Transactions on Computers.

Design of partially parallel scan chain

Kozo Kinoshita, Yoshinobu Higami, 1997, Proceedings European Design and Test Conference. ED & TC 97.

Crosstalk fault reduction and simulation for clock-delayed domino circuits

Kozo Kinoshita, Kazuya Shimizu, Noriyoshi Itazaki, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

An efficient procedure for obtaining implication relations and its application to redundancy identification

Kozo Kinoshita, Seiji Kajihara, Hideyuki Ichihara, 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

A Reduced Scan Shift Method for Sequential Circuit Testing (Special Section on VLSI Design and CAD Algorithms)

Kozo Kinoshita, Yoshinobu Higami, Seiji Kajihara, 1994 .