Hironori Banba

Wordline voltage generating system for low-power low-voltage flash memories

Hitoshi Shiga, Toru Tanzawa, Akira Umezawa, 2001 .

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus

H. Takato, Shinji Miyano, Ryo Fukuda, 1999 .

TP 2.6: A 3.3V-only 16Mb Flash Memory with Row-Decoding Scheme

Akira Umezawa, Masao Kuriyama, Hironori Banba, 1996 .

A CMOS band-gap reference circuit with sub 1 V operation

Hitoshi Shiga, Toru Tanzawa, Koji Sakui, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation

S. Yamada, Akira Umezawa, Masao Kuriyama, 1994 .

A 5 V-only 0.6 mu m flash EEPROM with row decoder scheme in triple-well structure

S. Yamada, Sumio Tanaka, Akira Umezawa, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure

S. Yamada, Sumio Tanaka, Akira Umezawa, 1992 .