Atsushi Kurokawa

发表

Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills

Atsushi Kurokawa, Akira Kasebe, Yasuaki Inoue, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Clock skew reduction for stacked chips using multiple source buffers

Atsushi Kurokawa, Masashi Imai, Nanako Niioka, 2015, 2015 15th International Symposium on Communications and Information Technologies (ISCIT).

Modeling the overshooting effect of multi-input gate in nanometer technologies

Atsushi Kurokawa, Zhangcai Huang, Yasuaki Inoue, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model

Atsushi Kurokawa, Zhangcai Huang, Yasuaki Inoue, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs

Atsushi Kurokawa, Masashi Imai, Kaoru Furumi, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

インダクタンス逆行列を用いた三次元集積回路の貫通シリコンビア間結合容量抽出;インダクタンス逆行列を用いた三次元集積回路の貫通シリコンビア間結合容量抽出;Coupling Capacitance Extraction between TSVs in 3D ICs Using Inverse of Inductance Matrix

Masa-aki Fukase, Atsushi Kurokawa, Tetsuya Kobayashi, 2015 .

Thermal placement on PCB of components including 3D ICs

Atsushi Kurokawa, Toshiki Kanamoto, Ryosuke Watanabe, 2020, IEICE Electron. Express.

Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew

Atsushi Kurokawa, Zhangcai Huang, Yasuaki Inoue, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF

Atsushi Kurokawa, Masanori Hashimoto, Hiroyuki Kobayashi, 2003, ASP-DAC '03.

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies

Atsushi Kurokawa, Masanori Hashimoto, Zhangcai Huang, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Neural Network-Based 3D IC Interconnect Capacitance Extraction

Atsushi Kurokawa, Toshiki Kanamoto, Koutaro Hachiya, 2019, 2019 2nd International Conference on Communication Engineering and Technology (ICCET).

Impact of Self-Heating in Wire Interconnection on Timing

Atsushi Kurokawa, Masanori Hashimoto, Hiroo Masuda, 2010, IEICE Trans. Electron..

A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills

Atsushi Kurokawa, Akira Kasebe, Yasuaki Inoue, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations

Nobuto Ono, Atsushi Kurokawa, Masanori Hashimoto, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Approximate formulae approach for efficient inductance extraction

Atsushi Kurokawa, Hiroo Masuda, Takashi Sato, 2003, ASP-DAC '03.

Simple Analytical Formulas for Estimating IR-Drops in an Early Design Stage

Atsushi Kurokawa, Kazuyuki Ooya, Yuji Takashima, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads

Atsushi Kurokawa, Zhangcai Huang, Yasuaki Inoue, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Capacitance and yield evaluations using a 90-nm process technology based on the dense power-ground interconnect architecture

Nobuto Ono, Atsushi Kurokawa, Yasuaki Inoue, 2005, Sixth international symposium on quality electronic design (isqed'05).

Wireless Power Transfer System with Long Wired Repeater

Atsushi Kurokawa, Motoki Ishizaki, 2018, 2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM).

An advanced effective capacitance model considering input waveform effect (第21回回路とシステム軽井沢ワークショップ論文集) -- (ばらつき関連技術)

Atsushi Kurokawa, Zhangcai Huang, Minglu Jiang, 2008 .

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills

Atsushi Kurokawa, Akira Kasebe, Zhangcai Huang, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Effective capacitance for gate delay with RC loads

Atsushi Kurokawa, Zhangcai Huang, Yasuaki Inoue, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Effect of substrate contacts on reducing crosstalk noise between TSVs

Atsushi Kurokawa, Masashi Imai, Masayuki Watanabe, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Development of a next generation ubiquitous processor chip

Tomoaki Sato, Atsushi Kurokawa, Masa-Aki Fukase, 2011, 2011 International Symposium on Intelligent Signal Processing and Communications Systems (ISPACS).

A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process and Environmental Variability

Atsushi Kurokawa, Masanori Hashimoto, Takao Onoye, 2006, IEEE/ACM International Conference on Computer-Aided Design.

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability

Atsushi Kurokawa, Masanori Hashimoto, Hiroo Masuda, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Structure optimization for timing in nano scale FinFET

Atsushi Kurokawa, Takashi Hasegawa, Toshiki Kanamoto, 2015, IEICE Electron. Express.

Dummy filling methods for reducing interconnect capacitance and number of fills

Atsushi Kurokawa, Akira Kasebe, Yasuaki Inoue, 2005, Sixth international symposium on quality electronic design (isqed'05).

DEPOGIT: dense power-ground interconnect architecture for physical design integrity

Nobuto Ono, Atsushi Kurokawa, Hiroo Masuda, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Efficient capacitance extraction method for interconnects with dummy fills

Atsushi Kurokawa, Akira Kasebe, Yasuaki Inoue, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies

Jing Wang, Atsushi Kurokawa, Zhangcai Huang, 2014, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

Optimum design of the execution stage of embedded processors

Atsushi Kurokawa, Masa-Aki Fukase, Tatsuya Takaki, 2012, 2012 International Symposium on Communications and Information Technologies (ISCIT).

Prevention in a Chip of EMI Noise Caused by X'tal Oscillator

Atsushi Kurokawa, Hiroshi Fujita, Tetsuya Ibe, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Modeling the overshooting effect of multi-input gate in nanometer technologies

Atsushi Kurokawa, Yasuaki Inoue, Li Ding, 2011 .

Modeling of substrate contacts in TSV-based 3D ICs

Atsushi Kurokawa, Masashi Imai, Masayuki Watanabe, 2014, 2014 International 3D Systems Integration Conference (3DIC).

Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays

Atsushi Kurokawa, Akira Kasebe, Zhangcai Huang, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Signal Propagation Delay Model in Vertically Stacked Chips

Atsushi Kurokawa, Masashi Imai, Masayuki Watanabe, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation

Atsushi Kurokawa, Masanori Hashimoto, Hiroyuki Kobayashi, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm

Atsushi Kurokawa, Yun Yang, Yasuaki Inoue, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies

Atsushi Kurokawa, Zhangcai Huang, Yasuaki Inoue, 2007, 2007 Asia and South Pacific Design Automation Conference.

An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs

Atsushi Kurokawa, Masashi Imai, Masayuki Watanabe, 2015, Sixteenth International Symposium on Quality Electronic Design.

Thermal Countermeasures of Glass Wearable Devices

Atsushi Kurokawa, Kodai Matsuhashi, 2019, 2019 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW).

Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability

Atsushi Kurokawa, Kazuyuki Ooya, Yuji Takashima, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Impact of on-chip interconnects on vertical signal propagation in 3D ICs

Atsushi Kurokawa, Masashi Imai, Masayuki Watanabe, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

ゲーテドクロックシステムへのNBTI起因デバイス劣化のインパクト;ゲーテドクロックシステムへのNBTI起因デバイス劣化のインパクト;Impact of Device Degradation Due to NBTI on Gated Clock Systems

Masayuki Watanabe, Atsushi Kurokawa, Makoto Hoshi, 2014 .

Challenge: variability characterization and modeling for 65- to 90-nm processes

Atsushi Kurokawa, Hiroo Masuda, Masakazu Aoki, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay

Atsushi Kurokawa, Zhangcai Huang, Yun Yang, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Thermal Management for Future Wrist Wearable Devices

Atsushi Kurokawa, Koudai Matsuhashi, 2018, 2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM).

A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis

Atsushi Kurokawa, Tomoyuki Nagase, Toshiki Kanamoto, 2020, IEICE Electron. Express.

An analytical model of the overshooting effect for multiple-input gates in nanometer technologies

Jing Wang, Atsushi Kurokawa, Zhangcai Huang, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect

Atsushi Kurokawa, Zhangcai Huang, Yasuaki Inoue, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Effective methods to promote heat dissipation of wrist wearables

Atsushi Kurokawa, Toshiki Kanamoto, Koutaro Hachiya, 2021 .

Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects

Atsushi Kurokawa, Hiroo Masuda, Kotaro Hachiya, 2003, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..