Chetan D. Parikh

发表

New technique to improve transient response of LDO regulators without an off-chip capacitor

Chetan D. Parikh, Gopal Agarwal, 2016, 2016 20th International Symposium on VLSI Design and Test (VDAT).

Novel Analog Calibration Technique for Current-Steering DACs

Chetan D. Parikh, Pallavi G. Darji, 2015, Circuits Syst. Signal Process..

A compact model for the N-well resistor

Rajendra Patrikar, Chetan D. Parikh, 1999 .

Low power and fast adder implementation with Double Gate MOSFETs

Amara Amara, Chetan D. Parikh, K. A. Shaik, 2011, 2011 Faible Tension Faible Consommation (FTFC).

Design of static latch based comparator using power constrained optimization

Chetan D. Parikh, A Purushothaman, 2010 .

Wake-up circuit for PAM4 receiver

Richa Gupta, Chetan D. Parikh, Vamsi Krishna Guduru, 2019, 2019 9th International Symposium on Embedded Computing and System Design (ISED).

Automating the design of Successive Approximation Register Analog to Digital Converters

Chetan D. Parikh, A Purushothaman, 2011 .

A 0.7-V rail-to-rail buffer amplifier with double-gate MOSFETs

Amara Amara, Chetan D. Parikh, D. Nagchoudhuri, 2011, 2011 Faible Tension Faible Consommation (FTFC).

Effect of Leakage Currents in Adiabatic Logic Circuits at Lower Technology Nodes

Chetan D. Parikh, Tridib Sarma, 2019, 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India).

10 Gbps Current Mode Logic I/O Buffer

Chetan D. Parikh, Akhil Rathore, 2013, VDAT.

A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier

Vivek Verma, Chetan D. Parikh, 2013, VDAT.

Low power high bandwidth amplifier with RC Miller and gain enhanced feedforward compensation

Vineet Kumar Singh, Shagun Bajoria, Chetan D. Parikh, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

A low power low area capacitor array based Digital to Analog Converter architecture

A. Purushothaman, Chetan D. Parikh, 2015, Microelectron. J..

A New Delay Model and Geometric Programming-Based Design Automation for Latched Comparators

A. Purushothaman, Chetan D. Parikh, C. Parikh, 2015, Circuits Syst. Signal Process..

Novel Analog Calibration Technique for Current-Steering DACs’ Dynamic Performance

Chetan D. Parikh, Pallavi G. Darji, 2016, Circuits Syst. Signal Process..

A Novel Architecture for Current-Steering Digital to Analog Converters

Chetan D. Parikh, Pallavi G. Darji, Maitry Upraity, 2012 .

A Calibration Technique for Current Steering DACs - Self Calibration with Capacitor Storage

Chetan D. Parikh, Pallavi G. Darji, 2017, VDAT.

Deterministic Digital Calibration of 1.5 bits/stage Pipelined ADCs by Direct Extraction of Calibration Coefficients

Subhajit Sen, Chetan D. Parikh, Chinmaye Ramamurthy, 2021, 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID).

Deterministic Digital Calibration Technique for 1.5 bits/stage Pipelined and Algorithmic ADCs with Finite op-amp Gain and Large Capacitance Mismatches

Subhajit Sen, Chetan D. Parikh, Chinmaye Ramamurthy, 2021, Circuits Syst. Signal Process..

Digital Calibration of 1.5 bits/stage Algorithmic ADC

Chetan D. Parikh, Chinmaye Ramamurthy, Subhajit Sen, 2021, 2021 18th International SoC Design Conference (ISOCC).

Modeling of the CoolMOS TM Transistor — Part I : Device Physics

Mahesh B. Patil, Chetan D. Parikh, Bobby J. Daniel, 2008 .

Modelling of a depletion-mode MOSFET

Juzer Vasi, Chetan D. Parikh, J. Vasi, 1987 .

A study of 100 nm channel length asymmetric channel MOSFET by using charge pumping

Souvik Mahapatra, Juzer Vasi, V. Ramgopal Rao, 1999 .

Modeling of the CoolMOS™ Transistor—Part II: DC Model and Parameter Extraction

Mahesh B. Patil, Chetan D. Parikh, Bobby J. Daniel, 2002 .

Magnetic field effects in a photoconductive switch

Fredrik A. Lindholm, Chetan D. Parikh, F. Lindholm, 1988 .

Performance and hot-carrier reliability of 100 nm channel length jet vapor deposited Si/sub 3/N/sub 4/ MNSFETs

Souvik Mahapatra, Juzer Vasi, Jason C. S. Woo, 2001 .

A comprehensive study of hot-carrier induced interface and oxide trap distributions in MOSFETs using a novel charge pumping technique

Souvik Mahapatra, Juzer Vasi, V. Ramgopal Rao, 2000 .

Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/ using theory of novel voltage sustaining layer

Mahesh B. Patil, Pravin N. Kondekar, Chetan D. Parikh, 2002, 2002 IEEE 33rd Annual IEEE Power Electronics Specialists Conference. Proceedings (Cat. No.02CH37289).

Analysis and design of superjunction power MOSFET: CoolMOS/spl trade/ for improved on resistance and breakdown voltage using theory of novel voltage sustaining layer

Mahesh B. Patil, Pravin N. Kondekar, Chetan D. Parikh, 2002, 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No.02TH8595).