E. Maciejewski

RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology

H. Kimura, E.J. Nowak, M. Gribelyuk, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

SMT and enhanced SPT with recessed SD to improve CMOS device performance

E. Maciejewski, E. Leobandung, J.J. Kim, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications

D. Daley, L. Wagner, S. Narasimha, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing

E. Maciejewski, D. Mocuta, M. Cai, 2008, 2008 IEEE International SOI Conference.

A 0.039um2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology

T. Kirihata, A. Blauberg, S. Narasimha, 2010, 2010 International Electron Devices Meeting.

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

G. Northrop, V. Sardesai, S. Narasimha, 2014, 2014 IEEE International Electron Devices Meeting.

(110) channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (Rext) engineering

S. Narasimha, E. Maciejewski, E. Leobandung, 2007, 2007 IEEE International Electron Devices Meeting.

Sub-60 nm physical gate length SOI CMOS

J. Sleight, E. Maciejewski, E. Nowak, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

S. Narasimha, J. Adkisson, E. Maciejewski, 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor

D. Mocuta, E. Maciejewski, E. Leobandung, 2008, 2008 IEEE International Electron Devices Meeting.