E. Leobandung

发表

RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology

H. Kimura, E.J. Nowak, M. Gribelyuk, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Synchronized Analog Capacitor Arrays for Parallel Convolutional Neural Network Training

E. Leobandung, M. J. Rasch, Y. Li, 2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS).

High-mobility high-Ge-content Si1−xGex-OI PMOS FinFETs with fins formed using 3D germanium condensation with Ge fraction up to x∼ 0.7, scaled EOT∼8.5Å and ∼10nm fin width

E. Leobandung, P. Hashemi, Takashi Ando, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Partially-depleted SOI technology for digital logic

E. Leobandung, G.G. Shahidi, F. Assaderaghi, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

SMT and enhanced SPT with recessed SD to improve CMOS device performance

E. Maciejewski, E. Leobandung, J.J. Kim, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Self-aligned III-V MOSFETs: Towards a CMOS compatible and manufacturable technology solution

E. Leobandung, D. K. Sadana, Y. Zhu, 2013, 2013 IEEE International Electron Devices Meeting.

Electron mobility in thin In0.53Ga0.47As channel

X. Sun, C.-C. Yeh, Martin M. Frank, 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

Etch patterning for advanced devices

E. Leobandung, 2015, Advanced Lithography.

Optimizing History Effects in 65nm PD-SOI CMOS

E. Leobandung, G. Freeman, M.M. Pelella, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS generation

M. Sherony, J. Sleight, G. Shahidi, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

Statistical measurement of random telegraph noise and its impact in scaled-down high-κ/metal-gate MOSFETs

M. Kobayashi, M. Yamaoka, E. Leobandung, 2012, 2012 International Electron Devices Meeting.

Capacitor-based Cross-point Array for Analog Neural Network with Record Symmetry and Linearity

E. Leobandung, Z. Ren, W. Haensch, 2018, 2018 IEEE Symposium on VLSI Technology.

Evaluation methodology for random telegraph noise effects in SRAM arrays

E. Leobandung, A. Bansal, H. Miki, 2011, 2011 International Electron Devices Meeting.

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

D. Mocuta, C. Norris, C. Radens, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

G. Biery, S. Narasimha, J. Adkisson, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Threshold voltage sensitivity of 0.1 /spl mu/m channel length fully-depleted SOI NMOSFET's with back-gate bias

E. Leobandung, Stephen Y. Chou, 1995 .

(110) channel, SiON gate-dielectric PMOS with record high Ion=1 mA/μm through channel stress and source drain external resistance (Rext) engineering

S. Narasimha, E. Maciejewski, E. Leobandung, 2007, 2007 IEEE International Electron Devices Meeting.

Si single-electron MOS memory with nanoscale floating-gate and narrow channel

E. Leobandung, S.Y. Chou, Langjie Guo, 1996, International Electron Devices Meeting. Technical Digest.

Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

D. Mocuta, S. Narasimha, A. Mocuta, 2002, Digest. International Electron Devices Meeting,.

A 7.9/5.5 psec room/low temperature SOI CMOS

E. Leobandung, L. Wagner, F. Assaderaghi, 1997, International Electron Devices Meeting. IEDM Technical Digest.

High performance and record subthreshold swing demonstration in scaled RMG SiGe FinFETs with high-Ge-content channels formed by 3D condensation and a novel gate stack process

T. Ando, V. Narayanan, E. Leobandung, 2017, 2017 Symposium on VLSI Technology.

Mainstreaming of the SOI technology

M. Sherony, E. Leobandung, D. Moy, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor

D. Mocuta, E. Maciejewski, E. Leobandung, 2008, 2008 IEEE International Electron Devices Meeting.

High performance 0.18 /spl mu/m SOI CMOS technology

M. Sherony, G. Biery, T.-C. Chen, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

A 0.25 /spl mu/m CMOS SOI technology and its application to 4 Mb SRAM

R. Flaker, S. Ratanaphanyarat, E. Leobandung, 1997, International Electron Devices Meeting. IEDM Technical Digest.

Channel doping impact on FinFETs for 22nm and beyond

P. Oldiges, T. B. Hook, T. Yamashita, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High-performance Si1−xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions

R. H. Dennard, E. Leobandung, P. Hashemi, 2013, 2013 Symposium on VLSI Technology.

Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT ∼7Å and scaled dimensions down to sub-4nm fin widths

T. Ando, V. Narayanan, E. Leobandung, 2016, 2016 IEEE Symposium on VLSI Technology.