Kyu-won Choi

Efficient I ns t ru ct io n -Level 0 pt i m izat i on M'e t hod0 logy for Low-Power Embedded Systems*

A. Chatterjee, Kyu-won Choi, 2001 .

Energy minimization of a pipelined processor using a low voltage pipelined cache

J.C. Park, V.J. Mooney, K. Palem, 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

Power-performance trade-offs in second level memory used by an ARM-like RISC architecture

Abhijit Chatterjee, Krishna V. Palem, Weng-Fai Wong, 2002 .

Efficient instruction-level optimization methodology for low-power embedded systems

Abhijit Chatterjee, Kyu-won Choi, A. Chatterjee, 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).