M. Linares-Aranda

Noise-tolerance improvement in dynamic CMOS logic circuits

F. Mendoza-Hernandez, M. Linares-Aranda, V. Champac, 2006 .

Energy-efficient high-speed CMOS pipelined multiplier

M. Linares-Aranda, M. Aguirre-Hernandez, 2008, 2008 5th International Conference on Electrical Engineering, Computing Science and Automatic Control.

A noise tolerant technique for submicron dynamic digital circuits

M. Linares-Aranda, F. Mendoza-Hernández, 2007 .

A Comparison Between Noise-Immunity Design Techniques for Dynamic Logic Gates

F. Mendoza-Hernandez, M. Linares-Aranda, O. Gonzalez-Diaz, 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

High-frequency interconnect modeling for global signal networks

R. Torres-Torres, M. Linares-Aranda, O. Gonzalez-Diaz, 2009, 2009 52nd IEEE International Midwest Symposium on Circuits and Systems.

Fused timing analytical model for repeater insertion and optimization

M. Linares-Aranda, M. Aguirre-Hernandez, M. Salim-Maza, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

Differential transimpedance amplifiers for communications systems based on common-gate topology

A. Diaz-Sanchez, M. Linares-Aranda, J. Martinez-Castillo, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A Clock-Gated Pulse-Triggered D Flip-Flop for Low-Power High-Performance VLSI Synchronous Systems

M. Linares-Aranda, M. Aguirre-Hernandez, 2006, 2006 International Caribbean Conference on Devices, Circuits and Systems.

Experimental performance analysis of a CMOS amplifier considering different layout techniques

A. L. Herrera-May, M. Linares-Aranda, F. López-Huerta, 2014 .