Daniele Mangano

Skew Insensitive PhysicalLinksforNetworkon Chip

Marcello Coppola, Riccardo Locatelli, Daniele Mangano, 2006 .

Enabling dynamic and programmable QoS in SoCs

Daniele Mangano, Giovanni Strano, 2010, NoCArc '10.

A cache design for high performance embedded systems

Pierfrancesco Foglia, Cosimo Antonio Prete, Daniele Mangano, 2005, J. Embed. Comput..

GALS Networks on Chip: A New Solution for Asynchronous Delay-Insensitive Links

Giuseppe Campobello, Carmine Ciofi, Daniele Mangano, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Relieving physical issues in new NoC-based SoCs

Alberto Scandurra, Daniele Mangano, Carlo Pistritto, 2007, Nano-Net.

Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer

Alberto Scandurra, Daniele Mangano, Giuseppe Falconeri, 2007 .

Tuning D-Nuca Cache

Pierfrancesco Foglia, Cosimo Antonio Prete, Daniele Mangano, 2005 .

A NUCA model for embedded systems cache design

Pierfrancesco Foglia, Cosimo Antonio Prete, Daniele Mangano, 2005, 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005..

Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer

Alberto Scandurra, Daniele Mangano, Carlo Pistritto, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

The electronic device and the sensor device with low power consumption and intelligent related method

Natale Aiello, Daniele Mangano, Giulio Zoppi, 2016 .

Skew Insensitive Physical Links for Network on Chip

Luca Fanucci, Alberto Scandurra, Marcello Coppola, 2006, 2006 1st International Conference on Nano-Networks and Workshops.

Verfahren und System für mesochrone Kommunikationen in mehreren Taktdomänen und entsprechendes Computerprogrammprodukt

Daniele Mangano, Carmelo Pistritto, Giuseppe Guarnaccia, 2007 .