G. Gouget

7.4 Characterization & Modeling of Low Electric Field Gate-Induced-Drain-Leakage

Fabien Gilibert, Francois Agut, Andre Juge, 2004 .

Device level modeling challenges for circuit design methodology in presence of variability

Thierry Poiroux, A. Juge, G. Gouget, 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

New length scaling of current gain factor and characterization method for pocket implanted MOSFET's

Andre Juge, M. Minondo, G. Gouget, 2001, ICMTS 2001. Proceedings of the 2001 International Conference on Microelectronic Test Structures (Cat. No.01CH37153).

Analysis of Gate Current Wafer Level Variability in Advanced FD-SOI MOSFETs

Andre Juge, Krishna Pradeep, T. A. Karatsori, 2018, 2018 48th European Solid-State Device Research Conference (ESSDERC).

Is SOI CMOS A Promising Technology For SOCs In High Frequency Range

Romain Gwoziecki, Alain Chantre, Daniel Gloria, 2005 .

Ultra thin gate oxide characterization

David Roy, Frederic Monsieur, Fabien Gilibert, 2004 .

New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n+ poly gate

G. Guegan, S. Deleonibus, J. Pretet, 2008 .

Series resistance estimation and C(V) measurements on ultra thin oxide MOS capacitors

David Roy, Andre Juge, M. Minondo, 2003, International Conference on Microelectronic Test Structures, 2003..

DC and AC MOS transistor modelling in presence of high gate leakage and experimental validation

David Roy, Fabien Gilibert, Andre Juge, 2004 .

New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n+ poly gate

G. Guegan, S. Deleonibus, J. Pretet, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.