Palmer Dabbelt

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI

Elad Alon, Borivoje Nikolić, Brian Zimmer, 2017, IEEE Journal of Solid-State Circuits.

A 0.37mm2 LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5k FFT accelerator integrated with a RISC-V core in 16nm FinFET

Elad Alon, Borivoje Nikolic, James Dunn, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

System Integration of RISC-V Processors with FD-SOI

James C.Y. Dunn, Elad Alon, Philippe Flatresse, 2020 .

The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V pdf

David A. Patterson, Krste Asanovic, Christopher Celio, 2016, ArXiv.

Cyclist: Accelerating hardware development

Krste Asanovic, Jonathan Bachrach, Patrick Li, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC

Elad Alon, Borivoje Nikolic, Krste Asanovic, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

Hwacha Preliminary Evaluation Results , Version 3 . 8

Palmer Dabbelt, Colin Schmidt, Krste Asanović, 2015 .