P. Brianceau

Physical Understanding of Program Injection and Consumption in Ultra-Scaled SiN Split-Gate Memories

G. Ghibaudo, P. Boivin, D. Lafond, 2012, 2012 4th IEEE International Memory Workshop.

Layered HfSiON-based tunnel stacks for voltage reduction and improved reliability in TANOS memories

G. Ghibaudo, G. Pananakakis, G. Molas, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Rules-based correction strategies setup on sub-micrometer line and space patterns for 200mm wafer scale SmartNIL process within an integration process flow

H. Teyssedre, L. Pain, P. Brianceau, 2017, Advanced Lithography.

Experimental and theoretical understanding of Forming, SET and RESET operations in Conductive Bridge RAM (CBRAM) for memory stack optimization

G. Ghibaudo, J. Cluzel, C. Carabasse, 2014, 2014 IEEE International Electron Devices Meeting.

Nanoimprint, DSA, and multi-beam lithography: patterning technologies with new integration challenges

F. Delachat, M. May, H. Teyssedre, 2017, Advanced Lithography.