Yihong Lu

发表

Integration Issue of Tensile SiN Liner for Dual Stress Liner(DSL) in Gate-Last High-k/Metal Gate(HKMG) Process Flow

Qiang Xu, Tao Yang, Peizhen Hong, 2013 .

Selective wet etching in fabricating SiGe nanowires with TMAH solution for gate-all-around MOSFETs

A. Du, Jun Luo, Wenwu Wang, 2020, Journal of Materials Science: Materials in Electronics.

Fabrication and selective wet etching of Si0.2Ge0.8/Ge multilayer for Si0.2Ge0.8 channel gate-all-around MOSFETs

Jun Luo, Guilei Wang, Wenwu Wang, 2021 .

An effective self-test method for extracting thermal parameters of thermopile IR sensors

Jianyu Fu, Ying Hou, Yihong Lu, 2022, Measurement.

Wafer acceptance test structures for characterization of thermoelectric materials’ thermal conductivity of thermopile sensors

Jianyu Fu, Yihong Lu, Fan-fei Qu, 2023, Journal of Micromechanics and Microengineering.

Strong anti-strain capacity of CoFeB/MgO interface on electronic structure and state coupling*

Yaping Wu, Zhiming Wu, Junyong Kang, 2018 .

2.1: Invited Paper: 16.9‐Inch Flexible AMOLED Display with High Performance Top Gate Oxide TFT

Yuan-chun Wu, Weiran Cao, Zhenguo Lin, 2021 .

Investigation of TaN as the wet etch stop layer for HKMG-last integration in the 22 nm and beyond nodes CMOS technology

Tianchun Ye, Jun Luo, Jianfeng Gao, 2015 .

Investigation of Fabricated CMOS FishboneFETs and TreeFETs With Strained SiGe Nano-Fins on Bulk-Si Substrate

Jianfeng Gao, Xiaobin He, Lei Cao, 2023, IEEE Electron Device Letters.

Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

Tianchun Ye, Q. Liang, Hongyu Yu, 2015, IEEE Transactions on Electron Devices.