Renato Stefanelli

发表

A behavioral approach to testability analysis for neural networks

Vincenzo Piuri, Donatella Sciuto, Mariagiovanna Sami, 1992, Microprocess. Microprogramming.

Innovative design of CMOS fault tolerant structures

Donatella Sciuto, Renato Stefanelli, Cristiana Bolchini, 1995, Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI).

Fault tolerance in neural networks: theoretical analysis and simulation results

Vincenzo Piuri, Mariagiovanna Sami, Renato Stefanelli, 1991, [1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications.

Concurrently self-checking structures for Fsms

Donatella Sciuto, Mariagiovanna Sami, Renato Stefanelli, 1993, Microprocess. Microprogramming.

A multiplier with multiple error correction capability

Renato Stefanelli, Marco Annaratone, 1983, 1983 IEEE 6th Symposium on Computer Arithmetic (ARITH).

Reconfiguration techniques in the presence of faulty interconnections

Mariagiovanna Sami, Renato Stefanelli, F. Distante, 1989, [1989] Proceedings International Conference on Wafer Scale Integration.

A New Compact SD2 Positive Integer Triangular Array Division Circuit

Marco D. Santambrogio, Renato Stefanelli, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Concurrent error detection in parallel multipliers and complex arithmetic structures: remarks on the use of the 3N code

Vincenzo Piuri, Renato Stefanelli, 1991 .

CMOS reliability improvements through a new fault tolerant technique

Donatella Sciuto, Renato Stefanelli, Cristiana Bolchini, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

A semi-custom approach for digital implementation of neural networks

Mariagiovanna Sami, Renato Stefanelli, F. Distante, 1991 .

Optimization techniques for multiple output function synthesis

Donatella Sciuto, Renato Stefanelli, Giacomo Buonanno, 1991, Proceedings of the European Conference on Design Automation..

Fault-tolerance techniques in arrays for image processing

Renato Stefanelli, Roberto Negrini, 1986 .

A comment on an investigation into the skeletonization approach of Hilditch

Renato Stefanelli, 1986, Pattern Recognit..

Mapping Neural Nets onto Massively parallel Silicon Architectures: A Defect-Tolerance Solution

Mariagiovanna Sami, Renato Stefanelli, F. Distante, 1991 .

Multi-parallel convolvers

Vincenzo Piuri, Renato Stefanelli, Luigi Dadda, 1993, Proceedings of IEEE 11th Symposium on Computer Arithmetic.

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Yvon Savaria, Fabrizio Lombardi, Mariagiovanna Sami, 1993 .

Array partitioning to achieve defect tolerance

Mariagiovanna Sami, Renato Stefanelli, Fausto Distante, 1997, EUROMICRO 97. Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology (Cat. No.97TB100167).

Error detection in serial multipliers and in systolic arrays: An approach based upon A★N codes

Vincenzo Piuri, Renato Stefanelli, G. Tranverso, 1988, Microprocess. Microprogramming.

Synthesis of multiple outputs CMOS gates

Donatella Sciuto, Renato Stefanelli, Giacomo Buonanno, 1991, [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design.

Compression algorithms that preserve basic topological features in binary-coded patterns

Mariagiovanna Sami, Renato Stefanelli, M. Sami, 1973, Pattern Recognit..

Fault-tolerant CAM architectures: a design framework

Mariagiovanna Sami, Renato Stefanelli, Fabio Salice, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Fault detection and fault tolerance issues at CMOS level through AUED encoding

Donatella Sciuto, Renato Stefanelli, Cristiana Bolchini, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Testing of Processing Arrays

Mariagiovanna Sami, Renato Stefanelli, F. Distante, 1988 .

Dominance based methodologies for multiple output CMOS combinational gates synthesis

Donatella Sciuto, Renato Stefanelli, Giacomo Buonanno, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

A Proposal for Neural Macrocell Array

Renato Stefanelli, Mariagiovanna Sami, G. Storti Gajani, 1990 .

Reconfiguration of VLSI arrays: a technique for increased flexibility and reliability

Mariagiovanna Sami, Renato Stefanelli, V. G. Lazarev, 1985 .

Testing techniques for complex VLSI/WSI processing arrays

Mariagiovanna Sami, Renato Stefanelli, F. Distante, 1989 .

Use of redundant binary representation for fault-tolerant arithmetic array processors

Vincenzo Piuri, Renato Stefanelli, 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

Harvesting through array partitioning: a solution to achieve defect tolerance

Mariagiovanna Sami, Renato Stefanelli, Fausto Distante, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Fault-tolerance of cellular processing arrays: algorithmic methods for yield enhancement and reliability

Renato Stefanelli, V. G. Lazarev, V. N. Doniants, 1989 .

Static redundancy techniques for CMOS gates

Donatella Sciuto, Renato Stefanelli, Cristiana Bolchini, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

Systematic AUED codes for self-checking architectures

Cristina Silvano, Donatella Sciuto, Renato Stefanelli, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

Arithmetic codes for concurrent error detection in artificial neural networks: the case of AN+B codes

Vincenzo Piuri, Mariagiovanna Sami, Renato Stefanelli, 1992, Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

A Suggestion rora High-Speed ParallelBinary Divider

Renato Stefanelli, R. Stefanelli, 1972 .

Reconfiguration of VLSI arrays by covering

Fabrizio Lombardi, Mariagiovanna Sami, Renato Stefanelli, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An improved fault tolerant architecture at CMOS level

Donatella Sciuto, Renato Stefanelli, Cristiana Bolchini, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Fault tolerance in imaging-oriented systolic arrays

Mariagiovanna Sami, Renato Stefanelli, N. Scarabottolo, 1989 .

A general index mapping technique for array reconfiguration

Mariagiovanna Sami, Renato Stefanelli, F. Distante, 1988, 1988., IEEE International Symposium on Circuits and Systems.

Some Parallel Thinning Algorithms for Digital Pictures

Azriel Rosenfeld, Renato Stefanelli, A. Rosenfeld, 1971, JACM.

Fault-tolerant techniques for VLSI tree structures

Vincenzo Piuri, Renato Stefanelli, 1992 .

Radix-r Implementation of Neural Nets

Renato Stefanelli, A. Antola, G. C. Storti Gajani, 1990 .

Reconfigurable architectures for VLSl processing arrays

Renato Stefanelli, Mariagiovanna Sami, 1899 .

Innovative Structures for CMOS Combinational Gates Synthesis

Donatella Sciuto, Renato Stefanelli, Giacomo Buonanno, 1994, IEEE Trans. Computers.

KITE: a behavioural approach to fault-tolerance in FPGA-based systems

Mariagiovanna Sami, Renato Stefanelli, Giacomo R. Sechi, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Fault-tolerance through reconfiguration of VLSI and WSI awards

Mariagiovanna Sami, Renato Stefanelli, Roberto M. Negrini, 1989, MIT Press series in computer systems.

Interconnection Networks for Highly Parallel Supercomputing Architectures

Mariagiovanna Sami, Renato Stefanelli, A. Antola, 1990 .

Two architectures implementing feed-forward completely connected neural nets

Renato Stefanelli, 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

A new switching-level approach to multiple-output functions synthesis

Donatella Sciuto, Renato Stefanelli, Cristiana Bolchini, 1995, Proceedings of the 8th International Conference on VLSI Design.

Reconfigurable architectures for VLSI processing arrays

Renato Stefanelli, Mariagiovanna Sami, 1986 .

A Suggestion for a High-Speed Parallel Binary Divider

Renato Stefanelli, R. Stefanelli, 1972, IEEE Transactions on Computers.

Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays

Mariagiovanna Sami, Renato Stefanelli, R. Negrini, 1989 .

A digital Architecture for Neural Networks

Mariagiovanna Sami, Renato Stefanelli, F. Distante, 1993 .

Innovative Structures for CMOS

Donatella Sciuto, Renato Stefanelli, Giacomo Buonanno, 1994 .

A CMOS fault tolerant architecture for switch-level faults

Donatella Sciuto, Renato Stefanelli, Cristiana Bolchini, 1994, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

Designing ad-hoc codes for the realization of fault tolerant CMOS networks

Donatella Sciuto, Renato Stefanelli, Cristiana Bolchini, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

A configurable array architecture for WSI implementation of neural nets

Mariagiovanna Sami, Renato Stefanelli, F. Distante, 1990, Ninth Annual International Phoenix Conference on Computers and Communications. 1990 Conference Proceedings.

Neural networks on silicon: the mapping of hardware faults onto behavioral errors

Vincenzo Piuri, Mariagiovanna Sami, Renato Stefanelli, 1991, [Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems.

Fault-tolerant neural architectures: a general approach to concurrent diagnosis based on signature analysis

Vincenzo Piuri, Mariagiovanna Sami, Renato Stefanelli, 1993, Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan).

A behavioral approach to testability of neural networks

Vincenzo Piuri, Donatella Sciuto, Mariagiovanna Sami, 1992, [Proceedings 1992] IJCNN International Joint Conference on Neural Networks.

Fault Tolerance Techniques for Array Structures Used in Supercomputing

Mariagiovanna Sami, Renato Stefanelli, Roberto M. Negrini, 1986, Computer.

Fault-tolerance and reconfigurability issues in massively parallel architectures

Mariagiovanna Sami, Renato Stefanelli, F. Distante, 1995, Proceedings of Conference on Computer Architectures for Machine Perception.

A Technique for Reconfiguring Two Dimensional VLSI Arrays

Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli, 1987, RTSS.

PAPIA: Pyramidal architecture for parallel image analysis

Renato Stefanelli, Marco Ferretti, Virginio Cantoni, 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).

An algorithm for functional reconfiguration of fixed-size arrays

Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Reconfigurable architectures for VLSI processing arrays

Mariagiovanna Sami, Renato Stefanelli, M. Sami, 1983, Proceedings of the IEEE.

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

P. Bailly, Vincenzo Piuri, Franco Maloberti, 1995 .

A fault-tolerant multi-port associative memory scheme

Mariagiovanna Sami, Renato Stefanelli, L. Dadda, 1993, 1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration.

FERMI/spl minus/a new generation of electronic modules for large data acquisition arrays required by high energy physics

Guido Torelli, P. Bailly, Vincenzo Piuri, 1994 .

A Compact and Fast Silicon Implementation for Layered Neural Nets

Mariagiovanna Sami, Renato Stefanelli, G. Storti-Gajani, 1991 .

A digital front-end and readout microsystem for calorimetry at LHC

Guido Torelli, Vincenzo Piuri, Franco Maloberti, 1992 .