D. Moy

CMOS 0.5-micron unified digital array using full E-beam lithography

F. J. Hohn, C. L. Chen, L. K. Wang, 1987, 1987 Symposium on VLSI Circuits.

Technology Elements of a Common Platform Bulk Foundry Offering (Invited)

M. Angyal, T. Hook, A. Steegen, 2007, 2007 IEEE International Electron Devices Meeting.

A 0.5 μm fully scaled two-level metal fully planarized interconnect structure fabricated with X-ray lithography

D. Moy, L.K. Wang, D.E. Seeger, 1990, Digest of Technical Papers.1990 Symposium on VLSI Technology.

A 2 W, 65% PAE single-supply enhancement-mode power PHEMT for 3 V PCS applications

P. Chye, D. Moy, Der-Woei Wu, 1997, 1997 IEEE MTT-S International Microwave Symposium Digest.

Inverter performance of deep-submicrometer MOSFETs

R.H. Dennard, D. Moy, M.R. Wordeman, 1988, IEEE Electron Device Letters.

High performance 0.1 /spl mu/m CMOS devices with 1.5 V power supply

Yuan Taur, Keith A. Jenkins, P. J. Coane, 1993, Proceedings of IEEE International Electron Devices Meeting.

Experimental technology and characterization of self-aligned 0.1µm-gate-length low-temperature operation NMOS devices

D. Moy, D.S. Zicherman, E. Ganin, 1987, 1987 International Electron Devices Meeting.

Mainstreaming of the SOI technology

M. Sherony, E. Leobandung, D. Moy, 1999, 1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).

0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography

R. H. Dennard, P. J. Coane, Y. Taur, 1986, 1986 Symposium on VLSI Technology. Digest of Technical Papers.

High performance 0.18 /spl mu/m SOI CMOS technology

M. Sherony, G. Biery, T.-C. Chen, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).