K JhaNiraj

发表

3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits

N BhojAjay, V JoshiRajiv, K JhaNiraj, 2013 .

What is majority/minority network synthesis?

K JhaNiraj, 2008 .

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs

K JhaNiraj, GulerAbdullah, 2016 .

Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis

RaghunathanAnand, K JhaNiraj, LakshminarayanaGanesh, 2000 .

Secure reconfiguration of software-defined radio

RaghunathanAnand, K JhaNiraj, LiChunxiao, 2012 .

FinFET-based power simulator for interconnection networks

LeeChun-Yi, K JhaNiraj, 2008 .

Reversible logic synthesis with Fredkin and Peres gates

DonaldJames, K JhaNiraj, 2008 .

Automated Quantum Circuit Synthesis and Cost Estimation for the Binary Welded Tree Oracle

K JhaNiraj, GhoshMrityunjay, ChakrabartiAmlan, 2017 .

Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations

K JhaNiraj, TangAoxiang, GaoXun, 2016 .

Energy-optimizing source code transformations for operating system-driven embedded software

RaghunathanAnand, K JhaNiraj, FeiYunsi, 2007 .

Analysis and design of a hardware/software trusted platform module for embedded systems

RaghunathanAnand, K JhaNiraj, AarajNajwa, 2009 .

Architectural support for run-time validation of program data properties

RaghunathanAnand, K JhaNiraj, RaviSrivaths, 2007 .

Energy-Efficient Graphical User Interface Design

K JhaNiraj, ZhongLin, S VallerioKeith, 2006 .

A defense framework against malware and vulnerability exploits

RaghunathanAnand, ZhangMeng, K JhaNiraj, 2014 .

A framework for defending embedded systems against software attacks

RaghunathanAnand, K JhaNiraj, AarajNajwa, 2011 .

Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits

K JhaNiraj, TangAoxiang, 2013 .

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology

N BhojAjay, K JhaNiraj, 2013 .

Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture

ZhangWei, K JhaNiraj, ShangLi, 2010 .

Energy-Efficient Long-term Continuous Personal Health Monitoring

Sur-KolaySusmita, RaghunathanAnand, Mozaffari-KermaniMehran, 2015 .

A hybrid nano/CMOS dynamically reconfigurable systemPart I

ZhangWei, K JhaNiraj, ShangLi, 2009 .

Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture

ZhangWei, K JhaNiraj, ShangLi, 2009 .

Express virtual channels

KumarAmit, PehLi-Shiuan, K JhaNiraj, 2007 .

Simultaneous dynamic voltage scaling of processors and communication links in real-time distributed embedded systems

PehLi-Shiuan, K JhaNiraj, LuoJiong, 2007 .

Memory binding for performance optimization of control-flow intensive behavioral descriptions

K JhaNiraj, LakshminarayanaGanesh, S KhouriKamal, 2005 .

FinFET-Based Power Management for Improved DPA Resistance with Low Overhead

ZhangMeng, K JhaNiraj, 2011 .

Generation of heterogeneous distributed architectures for memory-intensive applications through high-level synthesis

HuangChao, RaghunathanAnand, K JhaNiraj, 2007 .

Optimized Quantum Gate Library for Various Physical Machine Descriptions

K JhaNiraj, ChakrabartiAmlan, LinChia-Chun, 2013 .

Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment

K JhaNiraj, YuYe, 2017 .