Valery Axelrad

Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices

Manoj Sachdev, Hossein Sarbishaei, Oleg Semenov, 2006, Microelectron. J..

The Impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness

Manoj Sachdev, Hossein Sarbishaei, Oleg Semenov, 2004, Microelectron. Reliab..

Design and simulation of ESD-resistant ICs

Valery Axelrad, V. Axelrad, 2013, Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013.

Fourier method modeling of semiconductor devices

Valery Axelrad, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Grid quality and its influence on accuracy and convergence in device simulation

Valery Axelrad, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Design strategies for ESD protection in SOC

Artur Balasinski, Krzysztof Iniewski, Marek Syrzycki, 2004, 4th IEEE International Workshop on System-on-Chip for Real-Time Applications.

3.125 Gb/s power efficient line driver with 2-level pre-emphasis and 2 kV HBM ESD protection

Sebastian Magierowski, Artur Balasinski, Krzysztof Iniewski, 2005, 2005 IEEE International Symposium on Circuits and Systems.