R. P. Martins

Sensitivity aspects related to the switch timing of multirate switched-capacitor circuits

J. E. Franca, R. P. Martins, 1991, China., 1991 International Conference on Circuits and Systems.

Active feedback amplifier approach for microwave filter

Wai-Wa Choi, Kam-Weng Tam, R. P. Martins, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Interactive IIR SC Multirate Compiler Applied to Multistage decimator Design

R. P. Martins, PHILLIP N. CHEONG, P. N. Cheong, 2007, J. Circuits Syst. Comput..

A 2.4~ CMOS SWITCHED-CAPACITOR VIDEO DECIMATOR wl"H SAMPLING RATE REDUCI'ION FROM 40.5 NU32 TO 13.5 MHZ

R. P. Martins, 1989 .

A 79.1dB-SNDR 20MHz-BW 2nd-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture

Zhangming Zhu, Chi-Hang Chan, R. P. Martins, 2021, 2021 IEEE Custom Integrated Circuits Conference (CICC).

Split-based time-interleaved ADC with digital background timing-skew calibration

Sai-Weng Sin, U Seng-Pan, Mingqiang Guo, 2017, 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

26 / NYQUIST-RATE CONVERTERS / 26 . 5 26 . 5 A 5 . 5 mW 6 b 5 GS / s 4 ×-Interleaved 3 b / cycle SAR ADC in 65 nm CMOS

Sai-Weng Sin, U Seng-Pan, Chi-Hang Chan, 2015 .

Parasitic calibration by two-step ratio approaching technique for split capacitor array SAR ADCs

Sai-Weng Sin, Seng-Pan U, Chi-Hang Chan, 2009, 2009 International SoC Design Conference (ISOCC).

Optimum implementation of a multistage IIR SC bandpass decimator for a voiceband analogue interface system

J. E. Franca, R. P. Martins, 1988, 1988., IEEE International Symposium on Circuits and Systems.

A novel N-th order IIR switched-capacitor decimator building block with optimum implementation

J. E. Franca, R. P. Martins, 1989, IEEE International Symposium on Circuits and Systems,.