Kimiyoshi Usami

发表

Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET

Hideharu Amano, Hayate Okuhara, Yu Fujita, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Approximate Computing based on Latest-result Reuse for Image Edge Detection

Kimiyoshi Usami, Hajime Ochi, Yoshinori Ono, 2020, 2020 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Cong-Kha Pham, Kimiyoshi Usami, Hideharu Amano, 2014, 2014 IEEE Hot Chips 26 Symposium (HCS).

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Takashi Ishikawa, Kimiyoshi Usami, M. Takahashi, 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

Automated selective multi-threshold design for ultra-low standby applications

Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, 2002, ISLPED '02.

Datapath generator based on gate-level symbolic layout

Yoko Watanabe, Kimiyoshi Usami, Nobu Matsumoto, 1991, DAC '90.

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2012, 2012 International Conference on Field-Programmable Technology.

Clustered voltage scaling technique for low power

Kimiyoshi Usami, K. Usami, 1995 .

An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2016, IEICE Trans. Electron..

Selective Multi-Thershold Technique for High-Performance and Low-Standby Applications

Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, 2002 .

A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals

Kimiyoshi Usami, Naoaki Ohkubo, K. Usami, 2006, 2006 International Conference on Computer Design.

Building block multi-chip systems using inductive coupling through chip interface

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2017, 2017 International SoC Design Conference (ISOCC).

DESIGN METHODOLOGY OF STANDARD CELL LAYOUT AND PLA.

Jun Iwamura, Kimiyoshi Usami, Aya Ishii, 1987 .

Cool Mega-Array: A highly energy efficient reconfigurable accelerator

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2011, 2011 International Conference on Field-Programmable Technology.

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Hideharu Amano, Kimiyoshi Usami, Yusuke Yoshida, 2017, 2017 International SoC Design Conference (ISOCC).

On-chip detection methodology for break-even time of power gated function units

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

Clustered voltage scaling technique for low-power design

Mark Horowitz, Kimiyoshi Usami, M. Horowitz, 1995, ISLPED '95.

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Hideharu Amano, Kimiyoshi Usami, Yusuke Shuto, 2018, 2018 IEEE 7th Non-Volatile Memory Systems and Applications Symposium (NVMSA).

A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control

Hideharu Amano, Hayate Okuhara, Kimiyoshi Usami, 2015, 2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII).

Geyser: Energy-Efficient MIPS CPU Core with Fine-Grained Run-Time Power Gating

Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, 2012 .

Geyser

Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, 2012, Handbook of Energy-Aware and Green Computing.

Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router

Hideharu Amano, Kimiyoshi Usami, Hiroki Matsutani, 2012 .

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

Hideharu Amano, Hayate Okuhara, Yu Fujita, 2015, 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).

2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2013, VLSI-DAT.

MTJ Based Non-Volatile Flip Flop to Prevent Useless Store Operation

Kimiyoshi Usami, Masaru Kudo, 2015 .

Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI

Hideharu Amano, Kimiyoshi Usami, Shunsuke Kogure, 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction

Hideharu Amano, Kimiyoshi Usami, Masayuki Kimura, 2011, ARC.

Design of a 32 bit microprocessor, TX1

Jun Iwamura, Kimiyoshi Usami, M. Miyata, 1989 .

Foreword

Kimiyoshi Usami, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2011, 2011 IEEE Cool Chips XIV.

Hierarchical symbolic design methodology for large-scale datapaths

Kimiyoshi Usami, Nobu Matsumoto, Yukio Sugeno, 1990, IEEE Proceedings of the Custom Integrated Circuits Conference.

A fine-grain dynamic sleep control scheme in MIPS R3000

Hiroshi Nakamura, Hideharu Amano, Lei Zhao, 2008, 2008 IEEE International Conference on Computer Design.

Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating

Hiroshi Nakamura, Kimiyoshi Usami, Shinobu Miwa, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Effectiveness of Power Gating for a Superscalar processor

Kimiyoshi Usami, Tetsuya Muto, 2009 .

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2012, 17th Asia and South Pacific Design Automation Conference.

Power gating for FDSOI using dynamically body-biased power switch

Kimiyoshi Usami, Masaru Kudo, Yuichi Kumagai, 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

Foreword: Special section on VLSI design and CAD algorithms

Yuichiro Shibata, Makoto Ikeda, Hiroyuki Tomiyama, 2014 .

Power-Switch Clustering Method for Static Timing Analysis

Kimiyoshi Usami, T. Hashida, 2008 .

Methodologies for Power Gating

Kimiyoshi Usami, Takayasu Sakurai, T. Sakurai, 2006 .

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

Takashi Ishikawa, Tadahiro Kuroda, Mototsugu Hamada, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Energy Efficient Approximate Storing of Image Data for MTJ Based Non-volatile Memory

Kimiyoshi Usami, Yoshinori Ono, 2020, 2020 9th Non-Volatile Memory Systems and Applications Symposium (NVMSA).

Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems

Hideharu Amano, Kimiyoshi Usami, Hiroki Matsutani, 2016, IEICE Trans. Electron..

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Hideharu Amano, Kimiyoshi Usami, Weihan Wang, 2012, 2012 IEEE COOL Chips XV.

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Kimiyoshi Usami, Masaru Kudo, 2017, 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA).

Low-power design methodology and applications utilizing dual supply voltages

Kimiyoshi Usami, Mutsunori Igarashi, 2000, ASP-DAC.

Delay modeling and static timing analysis for MTCMOS circuits

Kimiyoshi Usami, Naoaki Ohkubo, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Kimiyoshi Usami, Takashi Ishikawa, Kazutaka Nogami, 1998 .

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2013 .

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Kimiyoshi Usami, Yusuke Yoshida, 2017, 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).

Adaptive power gating for function units in a microprocessor

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2011, IEEE Micro.

Hierarchical symbolic design methodology for large-scale data paths

Kimiyoshi Usami, Yukio Sugeno, Shojiro Mori, 1991 .

A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2015, IEICE Trans. Electron..

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2014, 2014 International Symposium on System-on-Chip (SoC).

Session details: Power estimation and design tradeoffs

Kimiyoshi Usami, Amitava Majumdar, Jerry Frenkil, 2005, DAC '05.

Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model

Hiroshi Nakamura, Kimiyoshi Usami, Kyundong Kim, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Low Power Technology in High-level Design

Kimiyoshi Usami, 2005 .

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

Hiroshi Nakamura, Hideharu Amano, Lei Zhao, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors

Hiroshi Nakamura, Hideharu Amano, Hiroaki Kobayashi, 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

A Thermal Management System for Building Block Computing Systems

Hideharu Amano, Yu Fujita, Kimiyoshi Usami, 2014, 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs.

Energy-Efficient Standard Cell Memory with Optimized Body-Bias Separation in Silicon-on-Thin-BOX (SOTB)

Kimiyoshi Usami, Yusuke Yoshida, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Low-power design technique for ASICs by partially reducing supply voltage

Kimiyoshi Usami, Masahiro Kanazawa, Takashi Ishikawa, 1996, Proceedings Ninth Annual IEEE International ASIC Conference and Exhibit.

Cache Controller Design on Ultra Low Leakage Embedded Processors

Hideharu Amano, Lei Zhao, Hui Xu, 2009, ARCS.

Circuit Structure of Level Shifter for Sub-threshold Operation

Kimiyoshi Usami, T. Ishizaki, 2010 .

Stepwise sleep depth control for run-time leakage power saving

Hiroshi Nakamura, Kimiyoshi Usami, Shinobu Miwa, 2012, GLSVLSI '12.

A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2013, IEEE Micro.

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2013, IEICE Trans. Electron..

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units (LSI Design Methodology Vol.4)

Zhao Lei, Kimiyoshi Usami, Daisuke Ikebuchi, 2011 .

A low-power design method using multiple supply voltages

Takashi Ishikawa, Kimiyoshi Usami, Takahiro Aoki, 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units

Hiroshi Nakamura, Zhao Lei, Hideharu Amano, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router

Hideharu Amano, Kimiyoshi Usami, Hiroki Matsutani, 2012, 2012 IEEE 6th International Symposium on Embedded Multicore SoCs.

Analysis on MTCMOS Circuits based on Lumped RC Model for Virtual Ground Line

Kimiyoshi Usami, Naoaki Ohkubo, K.Usami K.Usami, 2005 .

A clock-gating method for low-power LSI design

Kimiyoshi Usami, Toshiaki Ueda, Takeshi Kitahara, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique

Takashi Nishimura, Hideharu Amano, Kimiyoshi Usami, 2008, 2008 International Conference on Field-Programmable Technology.

Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits

Kimiyoshi Usami, Naoaki Ohkubo, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Geyser-2: The second prototype CPU with fine-grained run-time power gating

Hiroshi Nakamura, Hideharu Amano, Lei Zhao, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Design and evaluation of fine-grained power-gating for embedded microprocessors

Hiroshi Nakamura, Hideharu Amano, Hiroaki Kobayashi, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2013, 2013 IEEE Hot Chips 25 Symposium (HCS).

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect

Hiroshi Nakamura, Tadahiro Kuroda, Hideharu Amano, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

Prototyping of Operating System for Power-saving MIPS Processor and its Evaluation by Simulations

Kimiyoshi Usami, Hideharu Amano, Hiroshi Nakamura, 2008 .

A-3-8 Implementation and Analysis for Run-time Power Gating

Kimiyoshi Usami, Seidai Takeda, 2006 .

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode

Hideharu Amano, Cong-Kha Pham, Kazutoshi Kobayashi, 2015 .

Function-level power estimation methodology for microprocessors

Miodrag Potkonjak, Gang Qu, Kimiyoshi Usami, 2000, DAC.

Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI

Hideharu Amano, Kimiyoshi Usami, Shunsuke Kogure, 2017, VLSI-SoC.

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Hideharu Amano, Duc-Hung Le, Cong-Kha Pham, 2014, 2014 IEEE COOL Chips XVII.

Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Hideharu Amano, Kimiyoshi Usami, Kenta Suzuki, 2020, 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS).

Optimized design method for full-custom microprocessors

Jun Iwamura, Kimiyoshi Usami, 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

Apparatus and method for automatically generating circuits, and computer program product for executing the method

Kimiyoshi Usami, Masahiro Kanazawa, Naoyuki Kawabe, 2001 .

Power gating for ultra-low leakage: Physics, design, and analysis

Ken Choi, Kimiyoshi Usami, Jerry Frenkil, 2008, 2008 Design, Automation and Test in Europe.

Single Supply Level Shifter Circuit using body-bias

Kimiyoshi Usami, Yuki Takeyoshi, 2019, 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Implementation and evaluation of fine-grain run-time power gating for a multiplier

Kimiyoshi Usami, T. Shirai, H. Nakamura, 2009, 2009 IEEE International Conference on IC Design and Technology.

Low-power technique for on-chip memory using biased partitioning and access concentration

Kimiyoshi Usami, Naoyuki Kawabe, 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

Code Coverage-Based Power Estimation Techniques for Microprocessors

Miodrag Potkonjak, Gang Qu, Kimiyoshi Usami, 2002, J. Circuits Syst. Comput..

Optimal Design for Level-Shifter-Less Approach Using Channel Length Modulation & Body Biasing

Kimiyoshi Usami, Tatsuya Watanabe, 2020, 2020 35th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression

Hiroshi Nakamura, Hideharu Amano, Masashi Imai, 2009, 2009 22nd International Conference on VLSI Design.

Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs

Hiroshi Nakamura, Hideharu Amano, Kimiyoshi Usami, 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.

A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops

Hideharu Amano, Kimiyoshi Usami, Yusuke Shuto, 2018, 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

Overview on Low Power SoC Design Technology

Kimiyoshi Usami, 2007, 2007 Asia and South Pacific Design Automation Conference.

Approximate Computing Technique Using Memoization and Simplified Multiplication

Kimiyoshi Usami, Yoshinori Ono, 2019, 2019 34th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC).

Toward new developments of System and Signal Processing Subsociety

Isao Yamada, Kunihiko Hiraishi, Nagisa Ishiura, 2011 .

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Hideharu Amano, Kazutoshi Kobayashi, Kimiyoshi Usami, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Design and Analysis of On-chip Leakage Monitor using an MTCMOS circuit

Kimiyoshi Usami, Seidai Takeda, S. Koyama, 2008 .

Measurement of the minimum energy point in Silicon on Thin-BOX(SOTB) and bulk MOSFET

Kimiyoshi Usami, Shohei Nakamura, K. Usami, 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

International Conference on IC Design & Technology

Koji Eriguchi, Jen-Shiun Chiang, Kimiyoshi Usami, 2008 .

Level-shifter free approach for multi-Vdd SOTB employing adaptive Vt modulation for pMOSFET

Hideharu Amano, Kimiyoshi Usami, Shunsuke Kogure, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..