Jumpei Uchida

A thread partitioning algorithm in low power high-level synthesis

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

A thread partitioning algorithm in low power high-level synthesis

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

A High - level Synthesis Algorithm with Floorplaning for a Distributed - register Architecture

Masao Yanagisawa, Akira Tanaka, Tatsuo Ohtsuki, 2004 .

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2006, IEICE Trans. Electron..

Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

FPGA-Based Reconfigurable Adaptive FEC

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

High-level power optimization based on thread partitioning

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A processor core synthesis system in IP-based SoC design

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2005, ASP-DAC.