Khaled R. Heloue

Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models

Farid N. Najm, Khaled R. Heloue, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Parameterized timing analysis with general delay models and arbitrary variation sources

Farid N. Najm, Khaled R. Heloue, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Clock skew optimization via wiresizing for timing sign-off covering all process corners

Farid N. Najm, Khaled R. Heloue, Sari Onaissi, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths

Farid N. Najm, Khaled R. Heloue, Sari Onaissi, 2012, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation

Farid N. Najm, Khaled R. Heloue, Navid Azizi, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Efficient block-based parameterized timing analysis covering all potentially critical paths

Farid N. Najm, Khaled R. Heloue, Sari Onaissi, 2008, ICCAD 2008.

PSTA-based branch and bound approach to the silicon speedpath isolation problem

Farid N. Najm, Khaled R. Heloue, Sari Onaissi, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Early Analysis of Timing Margins and Yield

Farid N. Najm, Khaled R. Heloue, 2007, 2007 Canadian Conference on Electrical and Computer Engineering.

Statistical timing analysis with two-sided constraints

Farid N. Najm, Khaled R. Heloue, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation

Farid N. Najm, Khaled R. Heloue, Navid Azizi, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Quantifying robustness metrics in parameterized static timing analysis

Chandramouli V. Kashyap, Farid N. Najm, Khaled R. Heloue, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths

Farid N. Najm, Khaled R. Heloue, Sari Onaissi, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.