Harish Kriplani

Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution

Ibrahim N. Hajj, Farid N. Najm, Harish Kriplani, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits

Ibrahim N. Hajj, Ping Yang, Farid N. Najm, 1993, 30th ACM/IEEE Design Automation Conference.

Resource constrained design of artificial neural networks

Benjamin W. Wah, Harish Kriplani, 1990, 1990 IJCNN International Joint Conference on Neural Networks.

Worst case voltage drops in power and ground buses of CMOS VLSI circuits

Harish Kriplani, H. Kriplani, 1994 .

Maximum current estimation in CMOS circuits

Ibrahim N. Hajj, Farid N. Najm, Harish Kriplani, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Calculation of average and variance bus currents for reliability analysis of VLSI CMOS circuits

Ibrahim N. Hajj, Harish Kriplani, 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

Timing model extraction of hierarchical blocks by graph reduction

Harish Kriplani, Krishna P. Belkhale, Cho W. Moon, 2002, DAC '02.

Current Estimation for Electromigration, Hot Carriers, and Voltage Drop

Ibrahim N. Hajj, Harish Kriplani, Ping-Chung Li, 1994 .

Improved delay and current models for estimating maximum currents in CMOS VLSI circuits

Ibrahim N. Hajj, Farid N. Najm, Harish Kriplani, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.