Zheyu Yan

发表

Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?

X. Hu, Yiyu Shi, Zheyu Yan, 2022, 2207.07626.

On the Reliability of Computing-in-Memory Accelerators for Deep Neural Networks

X. Hu, Yiyu Shi, Zheyu Yan, 2022, ArXiv.

Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks

Meng Li, Weiwen Jiang, Hyoukjun Kwon, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search pdf

Yiyu Shi, Xiaobo Sharon Hu, Weiwen Jiang, 2021, 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC).

When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies

Masanori Hashimoto, Cheng Zhuo, Xichuan Zhou, 2019, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators

X. Hu, Yiyu Shi, J. Hu, 2019, IEEE Transactions on Computers.

On the Viability of Using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators

Yiyu Shi, Zheyu Yan, X. Hu, 2023, 2023 IEEE 36th International System-on-Chip Conference (SOCC).

Negative Feedback Training: A Novel Concept to Improve Robustness of NVCiM DNN Accelerators

Wujie Wen, Yiyu Shi, Zheyu Yan, 2023, ArXiv.

Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous?

X. Hu, Yiyu Shi, Zheyu Yan, 2022, 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

SWIM: selective write-verify for computing-in-memory neural accelerators

X. Hu, Yiyu Shi, Zheyu Yan, 2022, DAC.

Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search

Yiyu Shi, Xiaobo Sharon Hu, Da-Cheng Juan, 2021, 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC).

A Semi-Decoupled Approach to Fast and Optimal Hardware-Software Co-Design of Neural Accelerators

Yiyu Shi, Shaolei Ren, Zheyu Yan, 2022, ArXiv.

Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators Through Training with Right-Censored Gaussian Noise

Wujie Wen, Yi Shi, Zheyu Yan, 2023, 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD).

TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators

Zheyu Yan, X. Hu, Yiyu Shi, 2024, 2406.06544.

Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures

Dewen Zeng, Zhenge Jia, Zheyu Yan, 2024, ArXiv.

Compute-in-Memory based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections

Zheyu Yan, X. Hu, Yiyu Shi, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators

Zheyu Yan, X. Hu, Yiyu Shi, 2023, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.