Jonathan Rose

发表

VTR 7.0: Next Generation Architecture and CAD System for FPGAs

Sen Wang, Kenneth B. Kent, Vaughn Betz, 2014, TRETS.

A stochastic model to predict the routability of field-programmable gate arrays

Jonathan Rose, Stephen Dean Brown, Zvonko G. Vranesic, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Temperature measurement of simulated annealing placements

Jonathan Rose, Wolfgang Klebsch, Jürgen Wolf, 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

Generation of synthetic sequential benchmark circuits

Jonathan Rose, Mike Hutton, Derek G. Corneil, 1997, FPGA '97.

Logic emulation (panel): a niche or a future standard for design verification?

Jonathan Rose, 1993, DAC '93.

Routing for FPGAs

Jonathan Rose, Zvonko G. Vranesic, Stephen D. Brown, 1992 .

High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors

Vaughn Betz, Jonathan Rose, Henry Wong, 2016, 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy

Lothar Lilge, Jason Luu, Jonathan Rose, 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

The Transmogrifier-2: a 1 million gate rapid-prototyping system

Jonathan Rose, Paul Chow, David M. Lewis, 1998, IEEE Trans. Very Large Scale Integr. Syst..

Constraints from hell; how to tell makes a good FPGA (panel)

Sinan Kaptanoglu, Jonathan Rose, Rob Smith, 1998, FPGA '98.

Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency

Jonathan Rose, Paul Chow, David Lewis, 1990 .

VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling

Kenneth B. Kent, Jason Luu, Jonathan Rose, 2011, TRETS.

Using Architectural "Families" to Increase FPGA Speed and Density

Vaughn Betz, Jonathan Rose, 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

Measuring the Gap Between FPGAs and ASICs

Jonathan Rose, Ian Kuon, Jonathan Rose, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A detailed router for field-programmable gate arrays

Jonathan Rose, Stephen Dean Brown, Zvonko G. Vranesic, 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Theoretical Model for FPGA Routing

Jonathan Rose, Zvonko G. Vranesic, Stephen D. Brown, 1992 .

Definition And Solution Of The Memory Packing Problem For Field-programmable Systems

Jonathan Rose, David Karchmer, Jonathan Rose, 1994, IEEE/ACM International Conference on Computer-Aided Design.

The memory/logic interface in FPGAs with large embedded memory arrays

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic, 1999, IEEE Trans. Very Large Scale Integr. Syst..

Synthesizing datapath circuits for FPGAs with emphasis on area minimization

Jonathan Rose, David M. Lewis, Andy Ye, 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

A novel and efficient routing architecture for multi-FPGA systems

Jonathan Rose, Mohammed A. S. Khalid, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Cluster-Based Logic Blocks

Vaughn Betz, Jonathan Rose, Alexander Marquardt, 1999 .

Applications of clone circuits to issues in physical-design

Jonathan Rose, Mike Hutton, Jonathan Rose, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Equivalence classes of clone circuits for physical-design benchmarking

Jonathan Rose, Mike Hutton, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Technology Mapping for FPGAs

Jonathan Rose, Zvonko G. Vranesic, Stephen D. Brown, 1992 .

Structural analysis and generation of synthetic digital circuits with memory

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Automatic transistor and physical design of FPGA tiles from an architectural specification

Jonathan Rose, Ryan Fung, Ketan Padalia, 2003, FPGA '03.

Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits

Jonathan Rose, Andy Gean Ye, 2005, FPGA '05.

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect

Jason Luu, Jason Helge Anderson, Jonathan Rose, 2011, FPGA '11.

A fast routability-driven router for FPGAs

Vaughn Betz, Jonathan Rose, Jordan S. Swartz, 1998, FPGA '98.

Next-generation acceleration and code optimization for light transport in turbid media using GPUs

Stefan Andersson-Engels, Lothar Lilge, Jonathan Rose, 2010, Biomedical optics express.

Mixing buffers and pass transistors in FPGA routing architectures

Jonathan Rose, Mike Sheng, Jonathan Rose, 2001, FPGA '01.

Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System

Vaughn Betz, Jonathan Rose, Henry Wong, 2016, ACM Trans. Reconfigurable Technol. Syst..

Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design

Jonathan Rose, Ian Kuon, Jonathan Rose, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Verilog RTL synthesis tool for heterogeneous FPGAs

Jonathan Rose, Peter Jamieson, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Measuring and utilising the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks

Jonathan Rose, A. Ye, 2006 .

The Transmogrifier-4: an FPGA-based hardware development system with multi-gigabyte memory capacity and high host and memory bandwidth

Jonathan Rose, David R. Galloway, Joshua Fender, 2005, Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005..

Towards interconnect-adaptive packing for FPGAs

Jason Luu, Jason Helge Anderson, Jonathan Rose, 2014, FPGA.

Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters

Jonathan Rose, Peter Jamieson, Jonathan Rose, 2007, 2007 International Conference on Field-Programmable Technology.

GPU-accelerated Monte Carlo simulation for photodynamic therapy treatment planning

Lothar Lilge, Jonathan Rose, William Lo, 2009, European Conference on Biomedical Optics.

How Much Logic Should Go in an FPGA Logic Block?

Vaughn Betz, Jonathan Rose, Jonathan Rose, 1998, IEEE Des. Test Comput..

On the difficulty of pin-to-wire routing in FPGAs

Jonathan Rose, Niyati Shah, Jonathan Rose, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

Technology mapping of lookup table-based FPGAs for performance

Jonathan Rose, Zvonko G. Vranesic, Robert J. Francis, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

Chortle-crf: fast technology mapping for lookup table-based FPGAs

Jonathan Rose, Zvonko G. Vranesic, Robert J. Francis, 1991, 28th ACM/IEEE Design Automation Conference.

Logic Block Architecture

Jonathan Rose, Zvonko G. Vranesic, Stephen D. Brown, 1992 .

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture

Vaughn Betz, Jonathan Rose, Henry Wong, 2011, FPGA '11.

FPGA Architecture: Survey and Challenges

Russell Tessier, Jonathan Rose, Ian Kuon, 2008, Found. Trends Electron. Des. Autom..

VESPA: portable, scalable, and flexible FPGA-based vector processors

Jonathan Rose, J. Gregory Steffan, Peter Yiannacouras, 2008, CASES '08.

Automatic FPGA system and interconnect construction with multicast and customizable topology

Jonathan Rose, Alex Rodionov, 2015, 2015 International Conference on Field Programmable Technology (FPT).

Experimental Ev alua-tion of Mesh and Partial Crossbar Routing Architec-tures for Multi-FPGA Systems

Jonathan Rose, Mohammed A. S. Khalid, 1997 .

Soft vector processors vs FPGA custom hardware: measuring and reducing the gap

Jonathan Rose, J. Gregory Steffan, Peter Yiannacouras, 2009, FPGA '09.

Faster coevolution detection of proteins using maximum similar cliques

Jonathan Rose, Alex Rodionov, Alexandr Bezginov, 2010, BCB '10.

Structural analysis and generation of synthetic digital circuits with memory : Reconfigurable and Adaptive VLSI Systems

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic, 2001 .

The parallel decomposition and implementation of an integrated circuit global router

Jonathan Rose, 1988, PPoPP 1988.

An energy-efficient, fast FPGA hardware architecture for OpenCV-Compatible object detection

Jonathan Rose, Braiden Brousseau, 2012, 2012 International Conference on Field-Programmable Technology.

Routing Tools and Routing Architecture Generation

Vaughn Betz, Jonathan Rose, Alexander Marquardt, 1999 .

The Effect of Fixed I/O Pin Positioning on The Routability and Speed of FPGAs

Jonathan Rose, Mohammed A. S. Khalid, 1995 .

Automatic generation of FPGA routing architectures from high-level descriptions

Vaughn Betz, Jonathan Rose, Jonathan Rose, 2000, FPGA '00.

Routing and Logic Architecture

Vaughn Betz, Jonathan Rose, David Jefferson, 2003 .

Characterization and parameterized random generation of digital circuits

Jonathan Rose, Mike Hutton, Derek G. Corneil, 1996, DAC '96.

Synthetic circuit generation using clustering and iteration

Jonathan Rose, Paul D. Kundarewich, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters

Jonathan Rose, Peter Jamieson, Jonathan Rose, 2006, 2006 IEEE International Conference on Field Programmable Technology.

Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract)

Jonathan Rose, Jonathan Rose, 1991, DAC.

Design, layout and verification of an FPGA using automated tools

Jonathan Rose, Ian Kuon, Aaron Egier, 2005, FPGA '05.

A new, fast algorithm for detecting protein coevolution using maximum compatible cliques

Jonathan Rose, Alex Rodionov, Alexandr Bezginov, 2010, Algorithms for Molecular Biology.

Energy efficient object detection on the mobile GP-GPU

Jonathan Rose, Valeria Bertacco, Todd Austin, 2017, 2017 IEEE AFRICON.

Measuring the Gap Between FPGAs and ASICs

Jonathan Rose, Ian Kuon, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Session details: Technical Session 3: Architecture 1

Jonathan Rose, Jonathan Rose, 2015, FPGA 2015.

Commercially Available FPGAs

Jonathan Rose, Zvonko G. Vranesic, Stephen D. Brown, 1992 .

Temperature measurement and equilibrium dynamics of simulated annealing placements

Jonathan Rose, Wolfgang Klebsch, Jürgen Wolf, 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

SmartEye: An Accurate Infrared Eye Tracking System for Smartphones

Jonathan Rose, Moshe Eizenman, Braiden Brousseau, 2018, 2018 9th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON).

TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections

Jonathan Rose, Kevin Chung, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Hard vs. soft: the central question of pre-fabricated silicon

Jonathan Rose, Jonathan Rose, 2004, Proceedings. 34th International Symposium on Multiple-Valued Logic.

Introduction to FPGAs

Jonathan Rose, Zvonko G. Vranesic, Stephen D. Brown, 1992 .

FPGA routing architecture: segmentation and buffering to optimize speed and density

Vaughn Betz, Jonathan Rose, Jonathan Rose, 1999, FPGA '99.

Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits

Jonathan Rose, Andy Gean Ye, Jonathan Rose, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Exploration and Customization of FPGA-Based Soft Processors

Jonathan Rose, J. Gregory Steffan, Peter Yiannacouras, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Flexibility of FPGA Routing Architectures

Jonathan Rose, Zvonko G. Vranesic, Stephen D. Brown, 1992 .

Application-specific customization of soft processor microarchitecture

Jonathan Rose, J. Gregory Steffan, Peter Yiannacouras, 2006, FPGA '06.

Architectural and physical design challenges for one-million gate FPGAs and beyond

Dwight D. Hill, Jonathan Rose, 1997, FPGA '97.

Automatic generation of synthetic sequential benchmark circuits

Jonathan Rose, Mike Hutton, Derek G. Corneil, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Trading quality for compile time: ultra-fast placement for FPGAs

Jonathan Rose, Yaska Sankar, Jonathan Rose, 1999, FPGA '99.

Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density

Vaughn Betz, Jonathan Rose, Alexander Marquardt, 1999, FPGA '99.

Effect of the prefabricated routing track distribution on FPGA area-efficiency

Vaughn Betz, Jonathan Rose, Jonathan Rose, 1998, IEEE Trans. Very Large Scale Integr. Syst..

The stratixπ routing and logic architecture

Vaughn Betz, Jonathan Rose, David Jefferson, 2003, FPGA '03.

Portable, Flexible, and Scalable Soft

Jonathan Rose, J. Gregory Steffan, Peter Yiannacouras, 2012 .

Architecture of Centralized Field-Configurable Memory

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic, 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

Measuring and utilizing the correlation between signal connectivity and signal positioning for FPGAs containing multi-bit building blocks

Jonathan Rose, Andy Gean Ye, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Directional bias and non-uniformity in FPGA global routing architectures

Vaughn Betz, Jonathan Rose, 1996, Proceedings of International Conference on Computer Aided Design.

Directional bias and non-uniformity in FPGA global routing architectures

Vaughn Betz, Jonathan Rose, 1996, ICCAD 1996.

Synchronization Constraints for Interconnect Synthesis

Jonathan Rose, Alex Rodionov, 2017, FPGA.

Reconfigurable hardware implementation of a phase-correlation stereoalgorithm

W. James MacLean, Jonathan Rose, Ahmad Darabiha, 2006, Machine Vision and Applications.

Chortle: a technology mapping program for lookup table-based field programmable gate arrays

Jonathan Rose, Robert J. Francis, Kevin Chung, 1990, 27th ACM/IEEE Design Automation Conference.

Timing-driven placement for FPGAs

Vaughn Betz, Jonathan Rose, Alexander Marquardt, 2000, FPGA '00.

On Biased and Non-Uniform Global Routing Architectures and CAD Tools for FPGAs

Vaughn Betz, Jonathan Rose, Jonathan Rose, 1996 .

Field-programmable gate array architectures and algorithms optimized for implementing datapath circuits

Jonathan Rose, David Lewis, Andy Ye, 2004 .

Efficient methods for out-of-order load/store execution for high-performance soft processors

Vaughn Betz, Jonathan Rose, Henry Wong, 2013, 2013 International Conference on Field-Programmable Technology (FPT).

The effect of logic block architecture on FPGA performance

Jonathan Rose, Paul Chow, David Lewis, 1992 .

Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits

Jonathan Rose, Andy Gean Ye, Jonathan Rose, 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

Circuit design, transistor sizing and wire layout of FPGA interconnect

Vaughn Betz, Jonathan Rose, Jonathan Rose, 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

The VTR project: architecture and CAD for FPGAs from verilog to routing

Kenneth B. Kent, Jason Luu, Jeffrey B. Goeders, 2012, FPGA '12.

Automatic Topology Optimization for FPGA Interconnect Synthesis

Jonathan Rose, Alex Rodionov, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

Area and delay trade-offs in the circuit and architecture design of FPGAs

Jonathan Rose, Ian Kuon, Jonathan Rose, 2008, FPGA '08.

A Detailed Router for Field-Programmable Gate

Jonathan Rose, Zvonko G. Vranesic, Stephen D. Brown, 1992 .

Speed and area tradeoffs in cluster-based FPGA architectures

Vaughn Betz, Jonathan Rose, Alexander Marquardt, 2000, IEEE Trans. Very Large Scale Integr. Syst..

Real-time, frame-rate face detection on a configurable hardware system (poster abstract)

Jonathan Rose, Rob McCready, 2000, FPGA '00.

Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design

Vaughn Betz, Jonathan Rose, Henry Wong, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A synthesis oriented omniscient manual editor

Jonathan Rose, Tomasz S. Czajkowski, 2004, FPGA '04.

Portable, Flexible, and Scalable Soft Vector Processors

Jonathan Rose, J. Gregory Steffan, Peter Yiannacouras, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A high-speed ray tracing engine built on a field-programmable system

Jonathan Rose, Joshua Fender, Jonathan Rose, 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

Data parallel FPGA workloads: Software versus hardware

Jonathan Rose, J. Gregory Steffan, Peter Yiannacouras, 2009, 2009 International Conference on Field Programmable Logic and Applications.

Hybrid Eye-Tracking on a Smartphone with CNN Feature Extraction and an Infrared 3D Model

Jonathan Rose, Moshe Eizenman, Braiden Brousseau, 2020, Sensors.

Nearest neighbour interconnect architecture in deep submicron FPGAs

Jonathan Rose, A. Roopchansingh, Jonathan Rose, 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

On Hard Adders and Carry Chains in FPGAs

Bo Yan, Kenneth B. Kent, Vaughn Betz, 2014, FCCM 2014.

Global Routing Architecture

Vaughn Betz, Jonathan Rose, Alexander Marquardt, 1999 .

On Hard Adders and Carry Chains in FPGAs

Bo Yan, Sen Wang, Kenneth B. Kent, 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

A hybrid complete-graph partial-crossbar routing architecture for multi-FPGA systems

Jonathan Rose, Mohammed A. S. Khalid, Jonathan Rose, 1998, FPGA '98.

CAD Tools: Packing and Placement

Vaughn Betz, Jonathan Rose, Alexander Marquardt, 1999 .

Memory-to-memory connection structures in FPGAs with embedded memory arrays

Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic, 1997, FPGA '97.

LocusRoute: a parallel global router for standard cells

Jonathan Rose, 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

Characterization and parameterized generation of synthetic combinational benchmark circuits

J. P. Grossman, Jonathan Rose, Mike Hutton, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Definition and solution of the memory packing problem for field-programmable systems

Jonathan Rose, David Karchmer, 1994, ICCAD.

An SRAM-programmable field-configurable memory

Steven J. E. Wilton, Jonathan Rose, T. Ngai, 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

Synthesis methods for field programmable gate arrays

Jonathan Rose, Abbas El Gamal, Alberto Sangiovanni-Vincentelli, 1993 .

Portable and scalable FPGA-based acceleration of a direct linear system solver

Wei Zhang, Vaughn Betz, Jonathan Rose, 2008, 2008 International Conference on Field-Programmable Technology.

The Parallel Decomposition and Implementation of an Integrated Circuit Global Router

Jonathan Rose, 1988, PPOPP/PPEALS.

High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors

Vaughn Betz, Jonathan Rose, Henry Wong, 2018, ACM Trans. Reconfigurable Technol. Syst..

A detailed router for field-programmable gate arrays

Jonathan Rose, Stephen Dean Brown, Zvonko G. Vranesic, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

The effect of logic block complexity on area of programmable gate arrays

Jonathan Rose, Paul Chow, David Lewis, 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

The supersmall soft processor

Jonathan Rose, James Robinson, Sam Vafaee, 2010, 2010 VI Southern Programmable Logic Conference (SPL).

A parameterized automatic cache generator for FPGAs

Jonathan Rose, Peter Yiannacouras, Jonathan Rose, 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

Memory/logic interconnect flexibility in FPGAs with large embedded memory arrays

Steven J. E. Wilton, Jonathan Rose, Z. G. Vrancsic, 1996, Proceedings of Custom Integrated Circuits Conference.

Parallel standard cell placement algorithms with quality equivalent to simulated annealing

Jonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic, 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Hardware Accelerated Novel Protein Identification

Christopher W. V. Hogue, Jonathan Rose, Ruth Isserlin-Weinberger, 2004, FPL.

Improving FPGA routing architectures using architecture and CAD interactions

Jonathan Rose, Stephen Dean Brown, Benjamin Tseng, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems

Jonathan Rose, Mohammed A. S. Khalid, 1999, IPPS/SPDP Workshops.

VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling

Jason Luu, Jonathan Rose, Andy Ye, 2009, FPGA '09.

The Stratix II logic and routing architecture

Vaughn Betz, Jonathan Rose, David M. Lewis, 2005, FPGA '05.

Fine-grain performance scaling of soft vector processors

Jonathan Rose, J. Gregory Steffan, Peter Yiannacouras, 2009, CASES '09.

Invited Keynote 1: Closing the gap between FPGAs and ASICs

Jonathan Rose, Jonathan Rose, 2006, 2006 IEEE International Conference on Field Programmable Technology.

Fine-Grained Interconnect Synthesis

Jonathan Rose, Alex Rodionov, David Biancolin, 2015, FPGA.

Architectures and algorithms for field-programmable gate arrays with embedded memory

Steven J. E. Wilton, Jonathan Rose, Zvenko Vranesic, 1997 .

CALL FOR ARTICLES IEEE Design & Test of Computers Special Issue on Microprocessors

Jonathan Rose, Stephen Dean Brown, Jonathan Rose, 1996 .

EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits

Jonathan Rose, William Chow, Jonathan Rose, 2002, FPGA '02.

VPR: A new packing, placement and routing tool for FPGA research

Vaughn Betz, Jonathan Rose, Jonathan Rose, 1997, FPL.

Detailed Routing Architecture

Vaughn Betz, Jonathan Rose, Alexander Marquardt, 1999 .

Optimization of field-programmable gate array logic block architecture for speed

Jonathan Rose, Paul Chow, David Lewis, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

The Transmogrifier-2: a 1 million gate rapid prototyping system

Jonathan Rose, Paul Chow, David M. Lewis, 1997, FPGA '97.

The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop

Guy Lemieux, Jonathan Rose, 2011, FPGA '11.

Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs

Jonathan Rose, Ian Kuon, Aaron Egier, 2004, FPGA '04.

Video-rate stereo depth measurement on programmable hardware

W. James MacLean, Jonathan Rose, Ahmad Darabiha, 2003, 2003 IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 2003. Proceedings..

Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size

Vaughn Betz, Jonathan Rose, 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

FERMTOR: A Tunable Multiprocessor Architecture

Jonathan Rose, Zvonko G. Vranesic, Wayne M. Loucks, 1985, IEEE Micro.

Advantages of heterogeneous logic block architecture for FPGAs

Jonathan Rose, Jian-She He, Jonathan Rose, 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

Modeling routing demand for early-stage FPGA architecture development

Jonathan Rose, Wei Mark Fang, Jonathan Rose, 2008, FPGA '08.

Architecture and CAD for Deep-Submicron FPGAS

Vaughn Betz, Jonathan Rose, Alexander Marquardt, 1999, The Springer International Series in Engineering and Computer Science.

Portable and scalable FPGA-based acceleration of a direct linear system solver

Wei Zhang, Vaughn Betz, Jonathan Rose, 2008, 2008 International Conference on Field-Programmable Technology.

Taking the tester out of the SDMT: A proof of concept fully automated approach to assessing processing speed in people with MS

Jonathan Rose, Anthony Feinstein, Viral Prakash Patel, 2018, Multiple sclerosis.

A high-speed FPGA using programmable mini-tiles

Jonathan Rose, Paul Chow, Soon Ong Seo, 1993 .

Automated transistor sizing for FPGA architecture exploration

Jonathan Rose, Ian Kuon, Jonathan Rose, 2008, 2008 45th ACM/IEEE Design Automation Conference.

Performance characterization of mobile GP-GPUs

Jonathan Rose, Fitsum Assamnew Andargie, Jonathan Rose, 2015, AFRICON 2015.

Fine-Grained Interconnect Synthesis

Jonathan Rose, Alex Rodionov, David Biancolin, 2016, ACM Trans. Reconfigurable Technol. Syst..

The evolution of architecture exploration of programmable devices

Jonathan Rose, 2009, FPL.

Detection and Correspondence Matching of Corneal Reflections for Eye Tracking Using Deep Learning

Jonathan Rose, Moshe Eizenman, Braiden Brousseau, 2021, 2020 25th International Conference on Pattern Recognition (ICPR).

The Design of an SRAM-Based Field-Programmable Gate Array — Part I : Architecture

Jonathan Rose, Paul Chow, Kevin Chung, 1999 .

Patient Willingness to Consent to Mobile Phone Data Collection for Mental Health Apps: Structured Questionnaire

Jonathan Rose, Kathryn Fotinos, Martin Katzman, 2018, JMIR mental health.

Turning the tables: Loadable Kernel Module Rootkits deployed in a honeypot environment

Jonathan Rose, 2010 .