Shuou Nomura

A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation

Karthikeyan Sankaralingam, Shuou Nomura, Ranganathan Sankaralingam, 2010, 2010 IEEE International Test Conference.

A low-power multi-core media co-processor for mobile application processors

Shuou Nomura, Fumihiko Tachibana, Chen Kong Teh, 2009, 2009 IEEE International Conference on IC Design and Technology.

Relax: an architectural framework for software recovery of hardware faults

Karthikeyan Sankaralingam, Shuou Nomura, Marc de Kruijf, 2010, ISCA.

A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design

Mototsugu Hamada, Yoshinori Watanabe, Shuou Nomura, 2008, 2008 IEEE Custom Integrated Circuits Conference.

The Design, Modeling, and Evaluation of the Relax Architectural Framework

Karthikeyan Sankaralingam, Shuou Nomura, Marc de Kruijf, 2010 .

A unified model for timing speculation: Evaluating the impact of technology scaling, CMOS design style, and fault recovery mechanism

Karthikeyan Sankaralingam, Shuou Nomura, Marc de Kruijf, 2010, 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN).

Sampling + DMR: Practical and low-overhead permanent fault detection

Karthikeyan Sankaralingam, Shuou Nomura, Venkatraman Govindaraju, 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications

Shuou Nomura, Hirotsugu Kajihara, Tatsuo Shiozawa, 2021, Proc. VLDB Endow..