Ranganathan Sankaralingam

A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation

Karthikeyan Sankaralingam, Shuou Nomura, Ranganathan Sankaralingam, 2010, 2010 IEEE International Test Conference.

Controlling peak power during scan testing

Nur A. Touba, Ranganathan Sankaralingam, N. Touba, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Inserting test points to control peak power during scan testing

Nur A. Touba, Ranganathan Sankaralingam, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Reducing power dissipation during test using scan chain disable

Nur A. Touba, Ranganathan Sankaralingam, Bahram Pouya, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Static compaction techniques to control scan vector power dissipation

Nur A. Touba, Ranganathan Sankaralingam, Rama Rao Oruganti, 2000, Proceedings 18th IEEE VLSI Test Symposium.

Reducing test power during test using programmable scan chain disable

Nur A. Touba, Ranganathan Sankaralingam, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.