Tomohiro Ueno

A 60-GHz Sub-Sampling PLL Using A Dual-Step-Mixing ILFD,(invited)

Akira Matsuzawa, Tomohiro Ueno, Teerachot Siriburanon, 2014 .

A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI

Kenichi Okada, Akira Matsuzawa, Rui Wu, 2016, IEICE Trans. Electron..

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay

Kenichi Okada, Ning Li, Ahmed Musa, 2017, IEEE Journal of Solid-State Circuits.

3 A 64-QAM 60 GHz CMOS Transceiver with 4-Channel Bonding

Kenichi Okada, Akira Matsuzawa, Satoshi Kondo, 2013 .

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding

Kenichi Okada, Ahmed Musa, Akira Matsuzawa, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 2.2 GHz -242 dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture

Kenichi Okada, Akira Matsuzawa, Satoshi Kondo, 2016, IEEE Journal of Solid-State Circuits.

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

Kenichi Okada, Akira Matsuzawa, Satoshi Kondo, 2015, IEEE Journal of Solid-State Circuits.