岡田 健一

A 60-GHz Sub-Sampling PLL Using A Dual-Step-Mixing ILFD,(invited)

Akira Matsuzawa, Tomohiro Ueno, Teerachot Siriburanon, 2014 .

A -242dB FoM 4.2-mW ADC-PLL Using Digital Sub-Sampling Architecture

Akira Matsuzawa, 松澤 昭, 岡田 健一, 2015 .

A 64QAM 60GHz Transceiver with Automatic Image Calibration

Akira Matsuzawa, 松澤 昭, Kenichi Okada, 2016 .

An ADPLL-based High Interference Tolerant BLE Receiver with DAC Feedback Loop

Kenichi Okada, Akira Matsuzawa, Dexian Tang, 2018 .

C-12-9 A Fully Synthesized Fractional-N IL-PLL Using Only Digital Library

Akira Matsuzawa, Teerachot Siriburanon, Wei Deng, 2016 .